Lines Matching refs:im
66 immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
69 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
94 immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
98 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
99 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
101 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
104 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
107 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
108 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
111 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
112 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
113 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
114 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
115 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
116 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
117 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
118 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
119 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
123 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
171 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
181 clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
182 clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
