Lines Matching refs:im
32 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
36 out_be32(&im->sysconf.ddrlaw[0].bar,
38 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
39 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
41 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
42 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
45 out_be32(&im->ddr.cs_config[1], 0);
47 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
48 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
49 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
50 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
51 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
53 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
54 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
55 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
56 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
58 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
62 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
70 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
73 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
