Lines Matching refs:im
53 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
59 out_be32(&im->sysconf.ddrlaw[0].bar,
61 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
62 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
71 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
72 out_be32(&im->ddr.cs_config[0], config);
75 out_be32(&im->ddr.cs_config[1], 0);
76 out_be32(&im->ddr.cs_config[2], 0);
77 out_be32(&im->ddr.cs_config[3], 0);
79 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
80 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
81 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
82 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
84 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
85 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
87 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
88 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
90 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
91 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
96 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
123 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
124 fsl_lbc_t *lbc = &im->im_lbc;
127 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
