Lines Matching defs:enable
16 u32 enable;
22 enable = 1;
25 enable = 0;
40 en1.bits.en_clkmsmc = enable;
43 en1.bits.en_clkssi_s = enable;
46 en1.bits.en_clkssi_m = enable;
49 en1.bits.en_clksmc = enable;
52 en1.bits.en_clkebi = enable;
55 en1.bits.en_usbpll = enable;
58 en1.bits.en_clkusb60 = enable;
61 en1.bits.en_clkusb24 = enable;
64 en1.bits.en_clkuart2 = enable;
67 en1.bits.en_clkuart1 = enable;
70 en1.bits.en_clkperi20 = enable;
73 en2.bits.en_clkcpu = enable;
76 en1.bits.en_clk_i2s_dly = enable;
79 en1.bits.en_clk_scc_abp = enable;
82 en1.bits.en_clk_dtv_spdo = enable;
85 en1.bits.en_clkad = enable;
88 en1.bits.en_clkmvd = enable;
91 en1.bits.en_clktsd = enable;
94 en1.bits.en_clkga = enable;
97 en1.bits.en_clkdvp = enable;
100 en1.bits.en_clkmr2 = enable;
103 en1.bits.en_clkmr1 = enable;
132 u32 enable;
136 enable = 1;
139 enable = 0;
150 val.bits.swreset_clkmsmc = enable;
153 val.bits.swreset_clkssi_s = enable;
156 val.bits.swreset_clkssi_m = enable;
159 val.bits.swreset_clksmc = enable;
162 val.bits.swreset_clkebi = enable;
165 val.bits.swreset_clkusb60 = enable;
168 val.bits.swreset_clkusb24 = enable;
171 val.bits.swreset_clkuart2 = enable;
174 val.bits.swreset_clkuart1 = enable;
177 val.bits.swreset_pwm = enable;
180 val.bits.swreset_gpt = enable;
183 val.bits.swreset_i2c2 = enable;
186 val.bits.swreset_i2c1 = enable;
189 val.bits.swreset_gpio2 = enable;
192 val.bits.swreset_gpio1 = enable;
195 val.bits.swreset_clkcpu = enable;
198 val.bits.swreset_clk_i2s_dly = enable;
201 val.bits.swreset_clk_scc_abp = enable;
204 val.bits.swreset_clk_dtv_spdo = enable;
207 val.bits.swreset_clkad = enable;
210 val.bits.swreset_clkmvd = enable;
213 val.bits.swreset_clktsd = enable;
216 val.bits.swreset_clktsio = enable;
219 val.bits.swreset_clkga = enable;
222 val.bits.swreset_clkmpc = enable;
225 val.bits.swreset_clkcve = enable;
228 val.bits.swreset_clkdvp = enable;
231 val.bits.swreset_clkmr2 = enable;
234 val.bits.swreset_clkmr1 = enable;
