Lines Matching defs:rate
60 /* Get pll rate by id */
139 * GPLL rate from the SPL stage.
159 u32 div, con, con_id, rate;
192 rate = DIV_TO_RATE(pll_rate, div);
194 debug("%s: raw rate %d (post-divide by 2)\n", __func__, rate);
195 return rate >> 1;
199 ulong rate,
208 ulong rate;
210 { .mux = MMC_PLL_SEL_CPLL, .rate = CPLL_HZ },
211 { .mux = MMC_PLL_SEL_GPLL, .rate = GPLL_HZ },
212 { .mux = MMC_PLL_SEL_24M, .rate = 24 * MHz }
215 debug("%s: target rate %ld\n", __func__, rate);
218 * Find the largest rate no larger than the target-rate for
221 ulong parent_rate = parents[i].rate;
222 u32 div = DIV_ROUND_UP(parent_rate, rate);
226 debug("%s: rate %ld, parent-mux %d, parent-rate %ld, div %d\n",
227 __func__, rate, parents[i].mux, parents[i].rate, div);
237 /* This is our new best rate. */
249 static ulong rk3368_mmc_set_clk(struct clk *clk, ulong rate)
256 /* Find the best parent and rate */
257 rk3368_mmc_find_best_rate_and_parent(clk, rate << 1, &mux, &div);
321 /* An external clock will always generate the right rate... */
455 ulong rate = 0;
460 rate = rkclk_pll_get_rate(priv->cru, CPLL);
463 rate = rkclk_pll_get_rate(priv->cru, GPLL);
466 rate = rk3368_spi_get_clk(priv->cru, clk->id);
471 rate = rk3368_mmc_get_clk(priv->cru, clk->id);
475 rate = rk3368_saradc_get_clk(priv->cru);
481 return rate;
484 static ulong rk3368_clk_set_rate(struct clk *clk, ulong rate)
489 debug("%s id:%ld rate:%ld\n", __func__, clk->id, rate);
492 ret = rk3368_spi_set_clk(priv->cru, clk->id, rate);
496 ret = rk3368_ddr_set_clk(priv->cru, rate);
502 ret = rk3368_mmc_set_clk(clk, rate);
508 ret = rk3368_gmac_set_clk(priv->cru, rate);
512 ret = rk3368_saradc_set_clk(priv->cru, rate);
