Lines Matching refs:MHz
56 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
57 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
264 #define VCO_MAX_KHZ (3200 * (MHz / KHz))
265 #define VCO_MIN_KHZ (800 * (MHz / KHz))
266 #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
267 #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
286 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
389 if (best_diff_khz > 4 * (MHz/KHz)) {
391 "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz,
621 int aclk_vop = 198*MHz;
693 int aclk_emmc = 198*MHz;
703 /* use 24MHz source for 400KHz clock */
775 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
777 case 200*MHz:
781 case 300*MHz:
785 case 666*MHz:
789 case 800*MHz:
793 case 933*MHz:
