Lines Matching refs:ddr
22 * regs has the to-be-set values for DDR controller registers
23 * ctrl_num is the DDR controller number
27 * Dividing the initialization to two steps to deassert DDR reset signal
34 struct ccsr_ddr __iomem *ddr;
41 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
45 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
50 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
55 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
67 ddr_out32(&ddr->eor, regs->ddr_eor);
70 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
71 ddr_out32(&ddr->cs0_config, regs->cs[i].config);
72 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
75 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
76 ddr_out32(&ddr->cs1_config, regs->cs[i].config);
77 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
80 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
81 ddr_out32(&ddr->cs2_config, regs->cs[i].config);
82 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
85 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
86 ddr_out32(&ddr->cs3_config, regs->cs[i].config);
87 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
91 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
92 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
93 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
94 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
95 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
96 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
97 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
98 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
99 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
100 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
101 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
102 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
103 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
104 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
105 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
106 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
107 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
108 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
109 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
110 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
118 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
120 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
123 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
124 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
125 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
126 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
129 ddr_out32(&ddr->sdram_cfg_2,
131 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
132 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
135 ddr_out32(&ddr->ddr_cdr2,
140 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
141 ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
142 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
143 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
145 ddr_out32(&ddr->err_disable, regs->err_disable);
146 ddr_out32(&ddr->err_int_en, regs->err_int_en);
151 ddr_out32(&ddr->debug[i], regs->debug[i]);
158 * control register is set. Because all DDR components are connected to
172 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
176 * the DDR clock setup and the DDR config enable.
186 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
188 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
192 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
195 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
197 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
222 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
231 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
242 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
244 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
