Lines Matching refs:ddr
42 * regs has the to-be-set values for DDR controller registers
43 * ctrl_num is the DDR controller number
47 * Dividing the initialization to two steps to deassert DDR reset signal
54 struct ccsr_ddr __iomem *ddr;
75 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
79 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
84 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
89 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
102 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
105 ddr_out32(&ddr->eor, regs->ddr_eor);
107 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
112 ddr_out32(&ddr->cs0_bnds,
114 ddr_out32(&ddr->cs0_config,
118 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
119 ddr_out32(&ddr->cs0_config, regs->cs[i].config);
121 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
125 ddr_out32(&ddr->cs1_bnds,
128 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
130 ddr_out32(&ddr->cs1_config, regs->cs[i].config);
131 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
135 ddr_out32(&ddr->cs2_bnds,
138 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
140 ddr_out32(&ddr->cs2_config, regs->cs[i].config);
141 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
145 ddr_out32(&ddr->cs3_bnds,
148 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
150 ddr_out32(&ddr->cs3_config, regs->cs[i].config);
151 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
155 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
156 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
157 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
158 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
159 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
160 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
161 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
162 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
163 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
164 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
165 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
166 ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
167 ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
168 ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
169 ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
170 ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
171 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
172 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
173 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
174 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
175 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
176 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
177 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
178 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
179 ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
180 ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
181 ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
182 ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
183 ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
184 ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
185 ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
186 ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
187 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
189 ddr_out32(&ddr->sdram_interval,
192 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
194 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
195 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
203 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
205 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
208 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
209 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
210 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
211 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
212 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
213 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
214 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
217 ddr_out32(&ddr->sdram_cfg_2,
219 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
220 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
223 ddr_out32(&ddr->ddr_cdr2,
228 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
229 ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
230 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
231 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
238 ddr_out32(&ddr->ddr_sdram_rcw_2,
241 ddr_out32(&ddr->err_disable, regs->err_disable |
245 ddr_out32(&ddr->err_disable, regs->err_disable);
247 ddr_out32(&ddr->err_int_en, regs->err_int_en);
252 ddr_out32(&ddr->debug[i], regs->debug[i]);
260 ddr_out32(&ddr->ddr_cdr2,
263 temp32 = ddr_in32(&ddr->debug[28]);
265 ddr_out32(&ddr->debug[28], temp32);
266 ddr_out32(&ddr->debug[25], 0x9000);
269 ddr_out32(&ddr->debug[37], 1 << 31);
271 ddr_out32(&ddr->ddr_cdr2,
281 ddr_out32(&ddr->sdram_cfg_2,
286 temp32 = ddr_in32(&ddr->debug[25]);
289 ddr_out32(&ddr->debug[25], temp32);
295 temp32 = ddr_in32(&ddr->debug[28]);
296 ddr_out32(&ddr->debug[28], temp32 | 0x000a0000);
302 * control register is set. Because all DDR components are connected to
316 ddr_out32(&ddr->sdram_cfg, temp32);
320 * the DDR clock setup and the DDR config enable.
331 temp32 = ddr_in32(&ddr->sdram_cfg_2);
333 ddr_out32(&ddr->sdram_cfg_2, temp32);
337 temp32 = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
340 temp32 = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
342 ddr_out32(&ddr->sdram_cfg, temp32 | SDRAM_CFG_MEM_EN);
351 while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
358 ctrl_num, ddr_in32(&ddr->debug[1]));
379 set_wait_for_bits_clear(&ddr->sdram_md_cntl,
384 set_wait_for_bits_clear(&ddr->sdram_md_cntl,
389 set_wait_for_bits_clear(&ddr->sdram_md_cntl,
394 ddr_out32(&ddr->sdram_md_cntl, 0);
395 temp32 = ddr_in32(&ddr->debug[28]);
397 ddr_out32(&ddr->debug[28], temp32);
398 ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */
401 while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
408 ctrl_num, ddr_in32(&ddr->debug[1]));
420 set_wait_for_bits_clear(&ddr->sdram_md_cntl,
429 ddr_out32(&ddr->err_disable,
434 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
457 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
466 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
477 ddr_out32(&ddr->cs0_bnds, regs->cs[0].bnds);
479 ddr_out32(&ddr->cs1_bnds, regs->cs[1].bnds);
481 ddr_out32(&ddr->cs2_bnds, regs->cs[2].bnds);
483 ddr_out32(&ddr->cs3_bnds, regs->cs[3].bnds);
487 ddr_out32(&ddr->cs0_config, regs->cs[0].config);
491 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
497 temp32 = ddr_in32(&ddr->sdram_cfg_2);
499 ddr_out32(&ddr->sdram_cfg_2, temp32);
513 cs0_config = ddr_in32(&ddr->cs0_config);
514 cs0_bnds = ddr_in32(&ddr->cs0_bnds);
515 cs1_bnds = ddr_in32(&ddr->cs1_bnds);
516 cs2_bnds = ddr_in32(&ddr->cs2_bnds);
517 cs3_bnds = ddr_in32(&ddr->cs3_bnds);
520 ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
521 ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
522 ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
523 ddr_out32(&ddr
525 ddr_out32(&ddr->mtp1, BIST_PATTERN1);
526 ddr_out32(&ddr->mtp2, BIST_PATTERN1);
527 ddr_out32(&ddr->mtp3, BIST_PATTERN2);
528 ddr_out32(&ddr->mtp4, BIST_PATTERN2);
529 ddr_out32(&ddr->mtp5, BIST_PATTERN1);
530 ddr_out32(&ddr->mtp6, BIST_PATTERN1);
531 ddr_out32(&ddr->mtp7, BIST_PATTERN2);
532 ddr_out32(&ddr->mtp8, BIST_PATTERN2);
533 ddr_out32(&ddr->mtp9, BIST_PATTERN1);
534 ddr_out32(&ddr->mtp10, BIST_PATTERN2);
536 ddr_out32(&ddr->mtcr, mtcr);
541 mtcr = ddr_in32(&ddr->mtcr);
547 err_detect = ddr_in32(&ddr->err_detect);
548 err_sbe = ddr_in32(&ddr->err_sbe);
560 ddr_out32(&ddr->cs0_bnds, cs0_bnds);
561 ddr_out32(&ddr->cs1_bnds, cs1_bnds);
562 ddr_out32(&ddr->cs2_bnds, cs2_bnds);
563 ddr_out32(&ddr->cs3_bnds, cs3_bnds);
