Lines Matching refs:ddr
19 struct ccsr_ddr __iomem *ddr =
34 * Set the DDR IO receiver to an acceptable bias point.
49 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
50 out_be32(&ddr->cs0_config, regs->cs[i].config);
53 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
54 out_be32(&ddr->cs1_config, regs->cs[i].config);
57 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
58 out_be32(&ddr->cs2_config, regs->cs[i].config);
61 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
62 out_be32(&ddr->cs3_config, regs->cs[i].config);
66 out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
67 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
68 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
69 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
70 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
71 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
72 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
73 out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
74 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
75 out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
76 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
77 out_be32(&ddr->init_addr, regs->ddr_init_addr);
78 out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
82 * the DDR clock setup and the DDR config enable.
87 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
90 while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
