Lines Matching refs:dev_num
109 int ddr3_tip_reg_dump(u32 dev_num)
113 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
122 (dev_num, ACCESS_TYPE_UNICAST,
140 (dev_num, if_id,
151 (dev_num, if_id,
167 int ddr3_tip_init_config_func(u32 dev_num,
173 memcpy(&config_func_info[dev_num], config_func,
183 u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM])
207 int ddr3_tip_get_device_info(u32 dev_num, struct ddr3_device_info *info_ptr)
209 if (config_func_info[dev_num].tip_get_device_info_func != NULL) {
210 return config_func_info[dev_num].
211 tip_get_device_info_func((u8) dev_num, info_ptr);
313 int print_device_info(u8 dev_num)
318 CHECK_STATUS(ddr3_tip_get_device_info(dev_num, &info_ptr));
358 int ddr3_tip_print_log(u32 dev_num, u32 mem_addr)
375 ddr3_tip_run_sweep_test(dev_num, sweep_cnt, 1, is_pup_log);
376 ddr3_tip_run_sweep_test(dev_num, sweep_cnt, 0, is_pup_log);
379 ddr3_tip_run_leveling_sweep_test(dev_num, sweep_cnt, 0, is_pup_log);
380 ddr3_tip_run_leveling_sweep_test(dev_num, sweep_cnt, 1, is_pup_log);
383 ddr3_tip_print_all_pbs_result(dev_num);
384 ddr3_tip_print_wl_supp_result(dev_num);
386 CHECK_STATUS(ddr3_tip_restore_dunit_regs(dev_num));
387 ddr3_tip_reg_dump(dev_num);
526 int ddr3_tip_print_stability_log(u32 dev_num)
531 u32 max_cs = ddr3_tip_max_cs_get(dev_num);
558 (config_func_info[dev_num].tip_get_temperature != NULL)
559 ? (config_func_info[dev_num].
560 tip_get_temperature(dev_num)) : (0));
563 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x14c8,
568 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x17c8,
573 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x1dc8,
583 ddr3_tip_bus_read(dev_num, if_id,
591 ddr3_tip_bus_read(dev_num, if_id,
603 (dev_num, ACCESS_TYPE_UNICAST,
611 ddr3_tip_bus_read(dev_num, if_id,
624 ddr3_tip_bus_read(dev_num, if_id,
630 ddr3_tip_bus_read(dev_num, if_id,
637 ddr3_tip_bus_read(dev_num, if_id,
648 ddr3_tip_bus_read(dev_num, if_id,
658 ddr3_tip_bus_read(dev_num, if_id,
678 int ddr3_tip_register_xsb_info(u32 dev_num, struct hws_xsb_info *xsb_info_table)
680 memcpy(&xsb_info[dev_num], xsb_info_table, sizeof(struct hws_xsb_info));
687 int ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
692 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
704 CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id,
721 int ddr3_tip_write_adll_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
726 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
741 CHECK_STATUS(ddr3_tip_bus_write(dev_num,
756 int read_phase_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
761 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
769 CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id,
784 int write_leveling_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
789 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
799 CHECK_STATUS(ddr3_tip_bus_write(dev_num,
847 static int ddr3_tip_access_atr(u32 dev_num, u32 flag_id, u32 value, u32 **ptr);
851 u32 bus_cnt = 0, if_id, data_p1, data_p2, ui_data3, dev_num = 0;
852 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
861 (dev_num, if_id,
865 (dev_num, if_id, ACCESS_TYPE_UNICAST,
868 (dev_num, if_id, ACCESS_TYPE_UNICAST,
883 int ddr3_tip_set_atr(u32 dev_num, u32 flag_id, u32 value)
888 ret = ddr3_tip_access_atr(dev_num, flag_id, value, &ptr_flag);
904 static int ddr3_tip_access_atr(u32 dev_num, u32 flag_id, u32 value, u32 **ptr)
1233 int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM])
1236 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1249 int print_ph(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM])
1252 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1307 dev_num, u32 repeat_num, u32 direction,
1318 u32 max_cs = ddr3_tip_max_cs_get(dev_num);
1319 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1354 ddr3_tip_read_adll_value(dev_num, ctrl_adll,
1370 (dev_num, ACCESS_TYPE_MULTICAST, 0,
1373 hws_ddr3_run_bist(dev_num, sweep_pattern, res,
1375 /* ddr3_tip_reset_fifo_ptr(dev_num); */
1387 (dev_num,
1441 ddr3_tip_write_adll_value(dev_num, ctrl_adll, reg);
1443 ddr3_tip_read_adll_value(dev_num, ctrl_adll, reg, MASK_ALL_BITS);
1445 print_adll(dev_num, ctrl_adll);
1447 ddr3_tip_reset_fifo_ptr(dev_num);
1453 int ddr3_tip_run_leveling_sweep_test(int dev_num, u32 repeat_num,
1465 u32 max_cs = ddr3_tip_max_cs_get(dev_num);
1466 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1496 ddr3_tip_read_adll_value(dev_num, ctrl_adll, reg, 0x1f);
1497 read_phase_value(dev_num, ctrl_level_phase, reg, 0x7 << 6);
1500 ddr3_tip_read_adll_value(dev_num, ctrl_adll1,
1530 CHECK_STATUS(ddr3_tip_bus_write(dev_num,
1539 CHECK_STATUS(ddr3_tip_bus_write(dev_num,
1552 hws_ddr3_run_bist(dev_num, sweep_pattern, res, cs);
1553 ddr3_tip_reset_fifo_ptr(dev_num);
1559 CHECK_STATUS(ddr3_tip_if_read(dev_num,
1566 CHECK_STATUS(ddr3_tip_if_write(dev_num,
1572 CHECK_STATUS(ddr3_tip_if_write(dev_num,
1587 CHECK_STATUS(ddr3_tip_bus_write(dev_num, ACCESS_TYPE_UNICAST, if_id, pup_access, pup,
1590 CHECK_STATUS(ddr3_tip_bus_write(dev_num,
1632 write_leveling_value(dev_num, ctrl_adll, ctrl_level_phase, reg);
1634 ddr3_tip_write_adll_value(dev_num, ctrl_adll1, CTX_PHY_REG(cs));
1637 ddr3_tip_read_adll_value(dev_num, ctrl_adll, reg, MASK_ALL_BITS);
1639 print_adll(dev_num, ctrl_adll);
1640 print_ph(dev_num, ctrl_level_phase);
1642 ddr3_tip_reset_fifo_ptr(dev_num);
1651 u32 dev_num = 0;
1655 ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE));
1703 int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type,
1718 (dev_num, if_id, addr, 1,
1723 (dev_num, if_id, addr, 1,
1744 int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type,
