Lines Matching refs:dev_num
90 static int ddr3_tip_ddr3_training_main_flow(u32 dev_num);
91 static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,
93 static int ddr3_tip_ddr3_auto_tune(u32 dev_num);
96 static int odt_test(u32 dev_num, enum hws_algo_type algo_type);
99 int adll_calibration(u32 dev_num, enum hws_access_type access_type,
101 static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
207 static int ddr3_tip_pad_inv(u32 dev_num, u32 if_id);
208 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id);
213 int ddr3_tip_tune_training_params(u32 dev_num,
258 int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable)
268 (dev_num, ACCESS_TYPE_UNICAST, if_id,
275 (dev_num, ACCESS_TYPE_UNICAST, if_id,
282 (dev_num, ACCESS_TYPE_UNICAST, if_id,
288 (dev_num, ACCESS_TYPE_UNICAST, if_id,
297 (dev_num, ACCESS_TYPE_UNICAST, if_id,
303 (dev_num, ACCESS_TYPE_UNICAST, if_id,
314 int calc_cs_num(u32 dev_num, u32 if_id, u32 *cs_num)
321 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
352 int hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_prm)
365 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
376 CHECK_STATUS(ddr3_tip_configure_phy(dev_num));
396 (dev_num, ACCESS_TYPE_MULTICAST,
416 (dev_num, access_type, if_id,
422 (dev_num, access_type, if_id,
427 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
432 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
443 (dev_num, access_type, if_id,
448 (dev_num, access_type, if_id,
456 (dev_num, access_type, if_id,
460 (dev_num, access_type, if_id,
466 (dev_num, access_type, if_id,
468 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) < MV_TIP_REV_3) {
472 (dev_num, access_type, if_id,
512 ddr3_tip_configure_cs(dev_num, if_id, cs_cnt,
545 (dev_num, access_type, if_id,
549 (dev_num, access_type, if_id,
558 (dev_num, ACCESS_TYPE_MULTICAST,
575 (dev_num, access_type, if_id,
581 ddr3_tip_write_odt(dev_num, access_type, if_id,
583 ddr3_tip_set_timing(dev_num, access_type, if_id, freq);
585 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) < MV_TIP_REV_3) {
587 (dev_num, access_type, if_id,
592 (dev_num, access_type, if_id,
603 (dev_num, access_type, if_id,
616 (dev_num, if_id, &cs_num));
621 (dev_num, access_type, if_id,
625 (dev_num, access_type, if_id,
628 (dev_num, access_type, if_id,
634 (dev_num, access_type, if_id,
638 (dev_num, access_type, if_id,
643 (dev_num, access_type, if_id,
649 (dev_num, ACCESS_TYPE_MULTICAST,
653 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) == MV_TIP_REV_3) {
655 (dev_num, access_type, if_id,
659 (dev_num, access_type, if_id,
667 CHECK_STATUS(ddr3_tip_rank_control(dev_num, if_id));
670 CHECK_STATUS(ddr3_tip_pad_inv(dev_num, if_id));
675 (dev_num, access_type, if_id,
678 (dev_num, access_type, if_id,
686 ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap);
695 static int ddr3_tip_rev2_rank_control(u32 dev_num, u32 if_id)
698 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
743 (dev_num, ACCESS_TYPE_UNICAST, if_id, DDR3_RANK_CTRL_REG,
749 static int ddr3_tip_rev3_rank_control(u32 dev_num, u32 if_id)
752 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
776 (dev_num, ACCESS_TYPE_UNICAST, if_id, DDR3_RANK_CTRL_REG,
782 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id)
784 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_TIP_REV) == MV_TIP_REV_2)
785 return ddr3_tip_rev2_rank_control(dev_num, if_id);
787 return ddr3_tip_rev3_rank_control(dev_num, if_id);
793 static int ddr3_tip_pad_inv(u32 dev_num, u32 if_id)
796 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
804 ddr3_tip_bus_read_modify_write(dev_num, ACCESS_TYPE_UNICAST,
821 ddr3_tip_bus_read_modify_write(dev_num, ACCESS_TYPE_UNICAST,
859 int ddr3_tip_validate_algo_components(u8 dev_num)
879 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_dunit_mux_select_func,
881 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_dunit_write,
883 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_dunit_read,
885 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_phy_write,
887 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].mv_ddr_phy_read,
889 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_get_freq_config_info_func,
891 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_set_freq_divider_func,
893 status &= ddr3_tip_validate_algo_ptr(config_func_info[dev_num].tip_get_clock_ratio,
964 int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type)
976 return odt_test(dev_num, algo_type);
980 status = ddr3_tip_ddr3_auto_tune(dev_num);
1003 static int odt_test(u32 dev_num, enum hws_algo_type algo_type)
1025 ret = ddr3_tip_ddr3_auto_tune(dev_num);
1043 int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable)
1045 return config_func_info[dev_num].
1046 tip_dunit_mux_select_func((u8)dev_num, enable);
1052 int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access,
1055 config_func_info[dev_num].mv_ddr_dunit_write(reg_addr, mask, data_value);
1063 int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access,
1066 config_func_info[dev_num].mv_ddr_dunit_read(reg_addr, mask, data);
1074 dev_num, enum hws_access_type access_type,
1099 ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST,
1126 int ddr3_tip_bus_read(u32 dev_num, u32 if_id,
1130 return config_func_info[dev_num].
1137 int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type interface_access,
1142 return config_func_info[dev_num].
1150 int ddr3_tip_bus_read_modify_write(u32 dev_num, enum hws_access_type access_type,
1169 (dev_num, if_id, ACCESS_TYPE_UNICAST, phy_id,
1173 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1184 int adll_calibration(u32 dev_num, enum hws_access_type access_type,
1189 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1194 (dev_num, access_type, if_id, SDRAM_CFG_REG,
1198 (dev_num, access_type, if_id, SDRAM_CFG_REG,
1201 CHECK_STATUS(config_func_info[dev_num].
1202 tip_get_freq_config_info_func((u8)dev_num, frequency,
1208 (dev_num, access_type, if_id, bus_cnt,
1212 (dev_num, access_type, if_id, bus_cnt,
1219 (dev_num, ACCESS_TYPE_UNICAST, if_id, bus_cnt,
1223 (dev_num, ACCESS_TYPE_UNICAST, if_id, bus_cnt,
1230 (dev_num, access_type, if_id, DRAM_PHY_CFG_REG,
1234 (dev_num, access_type, if_id, DRAM_PHY_CFG_REG,
1238 if (ddr3_tip_if_polling(dev_num, access_type, if_id,
1247 (dev_num, access_type, if_id, SDRAM_CFG_REG,
1251 (dev_num, access_type, if_id, SDRAM_CFG_REG,
1257 int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type,
1273 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1279 ("dev %d access %d IF %d freq %d\n", dev_num,
1299 ddr3_tip_calc_cs_mask(dev_num, if_id, effective_cs,
1342 dev_num, access_type, if_id,
1364 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1372 (dev_num, access_type, if_id,
1376 (dev_num, access_type, if_id,
1381 (dev_num, access_type, if_id,
1385 (dev_num, access_type, if_id,
1391 (dev_num, access_type, if_id,
1394 (dev_num, access_type, if_id,
1397 (dev_num, access_type, if_id,
1400 (dev_num, access_type, if_id,
1406 (dev_num, access_type, if_id, DFS_REG, 0x4,
1409 if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST,
1423 CHECK_STATUS(calc_cs_num(dev_num, if_id, &cs_num));
1428 if (ddr3_tip_dev_attr_get(dev_num, MV_ATTR_INTERLEAVE_WA) == 1) {
1430 if (config_func_info[dev_num].tip_get_clock_ratio(frequency) == 1) {
1433 (dev_num, access_type, if_id,
1439 (dev_num, access_type, if_id,
1443 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1447 config_func_info[dev_num].tip_set_freq_divider_func(dev_num, if_id,
1452 (dev_num, access_type, if_id, DFS_REG,
1455 (dev_num, access_type, if_id, DFS_REG,
1464 (dev_num, access_type, if_id, DFS_REG,
1470 (dev_num, access_type, if_id, 0x1874,
1473 (dev_num, access_type, if_id, 0x1884,
1476 (dev_num, access_type, if_id, 0x1894,
1479 (dev_num, access_type, if_id, 0x18a4,
1485 (dev_num, access_type, if_id,
1489 (dev_num, access_type, if_id,
1493 CHECK_STATUS(config_func_info[dev_num].
1494 tip_get_freq_config_info_func(dev_num, frequency,
1502 (dev_num, ACCESS_TYPE_UNICAST,
1507 /*freq_mask[dev_num][frequency] << 8 */
1510 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1517 (dev_num, access_type, if_id,
1522 (dev_num, access_type, if_id,
1528 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x3ff03ff,
1537 (dev_num, access_type, if_id,
1541 (dev_num, access_type, if_id,
1545 ddr3_tip_set_timing(dev_num, access_type, if_id, frequency);
1548 ddr3_tip_cmd_addr_init_delay(dev_num, adll_tap);
1553 (dev_num, access_type, if_id, DFS_REG, 0,
1556 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x8, DFS_REG,
1564 (dev_num, access_type, if_id,
1567 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1f,
1575 (dev_num, access_type, if_id, DFS_REG, 0,
1579 (dev_num, access_type, if_id, DUNIT_MMASK_REG,
1587 (dev_num, access_type, if_id, MR0_REG,
1598 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1606 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1610 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1618 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DUNIT_ODT_CTRL_REG, 0xf, 0xf));
1621 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DUNIT_ODT_CTRL_REG,
1629 CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD0,
1634 CHECK_STATUS(ddr3_tip_write_mrs_cmd(dev_num, cs_mask, MR_CMD2,
1638 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1651 static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type,
1662 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1665 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1668 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type,
1675 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1684 static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type,
1706 t_hclk = MEGA / (freq_val[frequency] / config_func_info[dev_num].tip_get_clock_ratio(frequency));
1780 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1807 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1810 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1814 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
1818 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, DDR_TIMING_REG,
1832 int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info)
1836 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
1841 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
1846 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
1851 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
1856 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
1862 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
1874 int ddr3_tip_get_first_active_if(u8 dev_num, u32 interface_mask,
1894 int ddr3_tip_write_cs_result(u32 dev_num, u32 offset)
1897 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1910 ddr3_tip_bus_read(dev_num, if_id,
1916 ddr3_tip_bus_write(dev_num,
1934 int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, enum mr_number mr_num, u32 data, u32 mask)
1939 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1944 (dev_num, ACCESS_TYPE_UNICAST, if_id,
1951 if (ddr3_tip_if_polling(dev_num, ACCESS_TYPE_UNICAST, if_id, 0,
1965 int ddr3_tip_reset_fifo_ptr(u32 dev_num)
1970 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1976 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1980 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1984 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1987 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1991 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
1995 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
2004 int ddr3_tip_ddr3_reset_phy_regs(u32 dev_num)
2007 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
2016 (dev_num, ACCESS_TYPE_UNICAST,
2022 (dev_num, ACCESS_TYPE_UNICAST, if_id,
2027 (dev_num, ACCESS_TYPE_UNICAST, if_id,
2031 (dev_num, ACCESS_TYPE_UNICAST, if_id,
2035 (dev_num, ACCESS_TYPE_UNICAST, if_id,
2039 (dev_num, ACCESS_TYPE_UNICAST, if_id,
2043 (dev_num, ACCESS_TYPE_UNICAST, if_id,
2047 (dev_num, ACCESS_TYPE_UNICAST, if_id,
2051 (dev_num, ACCESS_TYPE_UNICAST, if_id,
2055 (dev_num, ACCESS_TYPE_UNICAST, if_id,
2065 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
2076 int ddr3_tip_restore_dunit_regs(u32 dev_num)
2082 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
2085 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
2089 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST,
2097 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
2106 int ddr3_tip_adll_regs_bypass(u32 dev_num, u32 reg_val1, u32 reg_val2)
2109 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
2117 (dev_num, ACCESS_TYPE_UNICAST, if_id,
2121 (dev_num, ACCESS_TYPE_UNICAST, if_id,
2133 static int ddr3_tip_ddr3_training_main_flow(u32 dev_num)
2142 u32 max_cs = ddr3_tip_max_cs_get(dev_num);
2148 CHECK_STATUS(print_device_info((u8)dev_num));
2152 ddr3_tip_validate_algo_components(dev_num);
2155 CHECK_STATUS(ddr3_tip_ddr3_reset_phy_regs(dev_num));
2165 config_func_info[dev_num].tip_set_freq_divider_func(
2166 (u8)dev_num, if_id, freq);
2175 adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq);
2181 ddr3_tip_reg_dump(dev_num);
2192 ret = hws_ddr3_tip_init_controller(dev_num, &init_cntr_prm);
2194 ddr3_tip_reg_dump(dev_num);
2204 ret = adll_calibration(dev_num, ACCESS_TYPE_MULTICAST, 0, freq);
2216 ddr3_tip_adll_regs_bypass(dev_num, 0, 0x1f);
2224 ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
2227 ddr3_tip_reg_dump(dev_num);
2240 ret = ddr3_tip_dynamic_write_leveling(dev_num, 1);
2242 ddr3_tip_reg_dump(dev_num);
2257 ret = ddr3_tip_load_all_pattern_to_mem(dev_num);
2259 ddr3_tip_reg_dump(dev_num);
2272 ddr3_tip_adll_regs_bypass(dev_num, phy_reg1_val, 0);
2286 ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
2289 ddr3_tip_reg_dump(dev_num);
2303 ret = ddr3_tip_dynamic_write_leveling(dev_num, 0);
2306 ret = ddr3_tip_legacy_dynamic_write_leveling(dev_num);
2310 ddr3_tip_reg_dump(dev_num);
2325 ret = ddr3_tip_load_all_pattern_to_mem(dev_num);
2327 ddr3_tip_reg_dump(dev_num);
2345 ret = ddr3_tip_dynamic_read_leveling(dev_num, medium_freq);
2348 ret = ddr3_tip_legacy_dynamic_read_leveling(dev_num);
2352 ddr3_tip_reg_dump(dev_num);
2365 ret = ddr3_tip_dynamic_write_leveling_supp(dev_num);
2367 ddr3_tip_reg_dump(dev_num);
2382 ret = ddr3_tip_pbs_rx(dev_num);
2384 ddr3_tip_reg_dump(dev_num);
2401 ret = ddr3_tip_pbs_tx(dev_num);
2403 ddr3_tip_reg_dump(dev_num);
2423 ret = ddr3_tip_freq_set(dev_num, ACCESS_TYPE_MULTICAST,
2434 ddr3_tip_reg_dump(dev_num);
2447 ret = ddr3_tip_dynamic_write_leveling(dev_num, 0);
2449 ddr3_tip_reg_dump(dev_num);
2461 ret = ddr3_tip_load_all_pattern_to_mem(dev_num);
2463 ddr3_tip_reg_dump(dev_num);
2476 ret = ddr3_tip_dynamic_read_leveling(dev_num, tm->
2480 ddr3_tip_reg_dump(dev_num);
2495 ddr3_tip_reg_dump(dev_num);
2512 ret = ddr3_tip_vref(dev_num);
2516 ddr3_tip_reg_dump(dev_num);
2535 ret = ddr3_tip_centralization_rx(dev_num);
2537 ddr3_tip_reg_dump(dev_num);
2556 ret = ddr3_tip_dynamic_write_leveling_supp(dev_num);
2558 ddr3_tip_reg_dump(dev_num);
2578 ret = ddr3_tip_centralization_tx(dev_num);
2580 ddr3_tip_reg_dump(dev_num);
2595 CHECK_STATUS(ddr3_tip_restore_dunit_regs(dev_num));
2598 ddr3_tip_reg_dump(dev_num);
2606 static int ddr3_tip_ddr3_auto_tune(u32 dev_num)
2619 status = ddr3_tip_ddr3_training_main_flow(dev_num);
2623 run_xsb_test(dev_num, xsb_validation_base_address, 1, 1,
2628 ddr3_tip_reg_dump(dev_num);
2631 CHECK_STATUS(ddr3_tip_print_log(dev_num, window_mem_addr));
2635 CHECK_STATUS(ddr3_tip_print_stability_log(dev_num));
2675 int ddr3_tip_enable_init_sequence(u32 dev_num)
2679 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
2683 CHECK_STATUS(ddr3_tip_if_write(dev_num, ACCESS_TYPE_MULTICAST, 0,
2690 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0, 0x1,
2712 (dev_num, ACCESS_TYPE_MULTICAST,
2721 int ddr3_tip_register_dq_table(u32 dev_num, u32 *table)
