Lines Matching refs:dev_num
23 typedef int (*HWS_TIP_DUNIT_MUX_SELECT_FUNC_PTR)(u8 dev_num, int enable);
25 u8 dev_num, enum hws_access_type interface_access, u32 if_id,
28 u8 dev_num, enum hws_access_type interface_access, u32 if_id,
31 u8 dev_num, enum hws_ddr_freq freq,
34 u8 dev_num, struct ddr3_device_info *info_ptr);
36 u8 dev_num, u32 cs_mask, struct hws_cs_config_info *cs_info);
38 u8 dev_num, u32 if_id, enum hws_ddr_freq freq);
39 typedef int (*HWS_GET_INIT_FREQ)(u8 dev_num, enum hws_ddr_freq *freq);
41 u32 dev_num, enum hws_access_type access_type, u32 dunit_id,
44 u32 dev_num, enum hws_access_type access_type, u32 dunit_id,
47 u32 dev_num, enum hws_access_type dunit_access_type, u32 if_id,
51 u32 dev_num, u32 if_id, enum hws_access_type phy_access_type,
54 u32 dev_num, enum hws_algo_type algo_type);
56 u32 dev_num, enum hws_access_type access_type, u32 if_id,
59 u32 dev_num, struct init_cntr_param *init_cntr_prm);
60 typedef int (*HWS_TRAINING_IP_PBS_RX_FUNC_PTR)(u32 dev_num);
61 typedef int (*HWS_TRAINING_IP_PBS_TX_FUNC_PTR)(u32 dev_num);
63 u32 dev_num, int enable);
65 u32 dev_num, struct mv_ddr_topology_map *tm);
67 u32 dev_num, enum hws_ddr_freq frequency,
70 u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data);
72 u32 dev_num, u32 if_id, u32 ddr_addr, u32 num_bursts, u32 *data);
74 u32 dev_num, enum hws_pattern pattern, enum hws_access_type access_type,
81 u32 dev_num, u32 if_id, struct bist_result *pst_bist_result);
82 typedef int (*HWS_TRAINING_IP_LOAD_TOPOLOGY)(u32 dev_num, u32 config_num);
83 typedef int (*HWS_TRAINING_IP_READ_LEVELING)(u32 dev_num, u32 config_num);
84 typedef int (*HWS_TRAINING_IP_WRITE_LEVELING)(u32 dev_num, u32 config_num);
85 typedef u32 (*HWS_TRAINING_IP_GET_TEMP)(u8 dev_num);
109 int ddr3_tip_init_config_func(u32 dev_num,
111 int ddr3_tip_register_xsb_info(u32 dev_num,
115 int print_device_info(u8 dev_num);
