Lines Matching defs:pup
49 static void ddr3_write_ctrl_pup_reg(int bc_acc, u32 pup, u32 reg_addr,
66 u32 reg, phase, delay, cs, pup;
108 for (pup = 0;
109 pup < dram_info->num_of_total_pups;
110 pup++) {
111 if (pup == dram_info->num_of_std_pups
113 pup = ECC_PUP;
116 pup);
121 dram_info->wl_val[cs][pup][P] = phase;
122 dram_info->wl_val[cs][pup][D] = delay;
123 dram_info->wl_val[cs][pup][S] =
127 cs, pup);
128 dram_info->wl_val[cs][pup][DQS] =
133 /* Debug message - Print res for cs[i]: cs,PUP,Phase,Delay */
137 for (pup = 0;
138 pup < dram_info->num_of_total_pups;
139 pup++) {
140 if (pup == dram_info->num_of_std_pups
142 pup = ECC_PUP;
143 DEBUG_WL_S("DDR3 - Write Leveling - PUP: ");
144 DEBUG_WL_D((u32) pup, 1);
147 dram_info->wl_val[cs][pup]
151 dram_info->wl_val[cs][pup]
186 u32 cs, cnt, pup_num, sum, phase, delay, max_pup_num, pup, sdram_offset;
240 DEBUG_WL_S("ECC PUP:\n");
242 DEBUG_WL_S("DATA PUP:\n");
291 /* Check pup which DQS/DATA is error */
292 for (pup = 0; pup < max_pup_num; pup++) {
294 pup_num = (ecc) ? ECC_PUP : pup;
295 if (pup < 4) { /* lower 32 bit */
296 tmp_pup = pup;
300 tmp_pup = pup - 4;
307 DEBUG_WL_S(" PUP: ");
317 + pup), 2);
324 pup) - sdram_pup_val;
332 pup);
337 /* PUP is correct - increment State */
359 pup * (1 - ecc) +
390 pup * (1 - ecc) +
395 pup = (ecc) ? max_pup_num : pup;
408 for (pup = 0; pup < dram_info->num_of_std_pups; pup++)
409 sum += dram_info->wl_val[cs][pup][S];
414 /* Checks if any pup is not locked after the change */
432 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) {
433 if (pup == dram_info->num_of_std_pups
435 pup = ECC_PUP;
436 reg = ddr3_read_pup_reg(PUP_WL_MODE, cs, pup);
474 u32 reg, phase, delay, cs, pup, pup_num;
486 /* Write to control PUP to Control Deskew Regs */
488 for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) {
491 ddr3_write_ctrl_pup_reg(1, pup, CNTRL_PUP_DESKEW + pup,
531 for (pup = 0;
532 pup < dram_info->num_of_total_pups;
533 pup++) {
534 if (pup == dram_info->num_of_std_pups
536 pup = ECC_BIT;
539 pup);
544 dram_info->wl_val[cs][pup][P] = phase;
545 dram_info->wl_val[cs][pup][D] = delay;
552 cs, pup, 0,
554 dram_info->wl_val[cs][pup][P] =
556 dram_info->wl_val[cs][pup][D] =
559 dram_info->wl_val[cs][pup][S] =
563 cs, pup);
564 dram_info->wl_val[cs][pup][DQS] =
570 * cs,PUP,Phase,Delay
575 for (pup = 0;
576 pup < dram_info->num_of_total_pups;
577 pup++) {
579 ("DDR3 - Write Leveling - PUP: ");
580 DEBUG_WL_D((u32) pup, 1);
583 dram_info->wl_val[cs][pup]
587 dram_info->wl_val[cs][pup]
606 /* Write to control PUP to Control Deskew Regs */
608 for (pup = 0; pup <= dram_info->num_of_total_pups;
609 pup++) {
610 ddr3_write_ctrl_pup_reg(1, pup,
611 CNTRL_PUP_DESKEW + pup, 0);
617 /* Configure Each PUP with locked leveling settings */
620 for (pup = 0;
621 pup < dram_info->num_of_total_pups;
622 pup++) {
624 pup_num = (pup == dram_info->num_of_std_pups) ?
625 ECC_BIT : pup;
635 /* Write to control PUP to Control Deskew Regs */
637 for (pup = 0; pup <= dram_info->num_of_total_pups;
638 pup++) {
639 ddr3_write_ctrl_pup_reg(1, pup,
640 CNTRL_PUP_DESKEW + pup, 0);
659 u32 reg, cs, cnt, pup, max_pup_num;
773 for (pup = 0; pup < max_pup_num; pup++) {
774 if (((res[cs] >> pup) & 0x1) == 0) {
776 pup, 1);
790 * each PUP Fail/Success
794 DEBUG_WL_FULL_C("DDR3 - Write Leveling - The Results: 1-PUP locked, 0-PUP failed -",
884 u32 reg, cs, cnt, pup;
902 /* Write to control PUP to Control Deskew Regs */
904 for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) {
907 ddr3_write_ctrl_pup_reg(1, pup, CNTRL_PUP_DESKEW + pup,
1025 * each PUP Fail/Success
1029 DEBUG_WL_FULL_C("DDR3 - Write Leveling - The Results: 1-PUP locked, 0-PUP failed -",
1101 /* Write to control PUP to Control Deskew Regs */
1103 for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) {
1104 ddr3_write_ctrl_pup_reg(1, pup, CNTRL_PUP_DESKEW + pup,
1127 u32 reg, pup_num, delay, phase, phaseMax, max_pup_num, pup,
1262 for (pup = 0; pup < (max_pup_num); pup++) {
1264 pup_num = (pup == dram_info->num_of_std_pups) ?
1265 ECC_BIT : pup;
1266 if (dram_info->wl_val[cs][pup][S] == 0) {
1267 /* Update phase to PUP */
1268 dram_info->wl_val[cs][pup][P] = phase;
1269 /* Update delay to PUP */
1270 dram_info->wl_val[cs][pup][D] = delay;
1278 && (dram_info->wl_val[cs][pup][S] == 0)) {
1280 * If the PUP is locked now and in last
1284 dram_info->wl_val[cs][pup][S] = 1;
1299 /* Debug message - Print res for cs[i]: cs,PUP,Phase,Delay */
1301 for (pup = 0; pup < (max_pup_num); pup++) {
1302 DEBUG_WL_S("DDR3 - Write Leveling - PUP: ");
1303 DEBUG_WL_D((u32) pup, 1);
1305 DEBUG_WL_D((u32) dram_info->wl_val[cs][pup][P], 1);
1307 DEBUG_WL_D((u32) dram_info->wl_val[cs][pup][D], 2);
1317 /* Configure Each PUP with locked leveling settings */
1318 for (pup = 0; pup < (max_pup_num); pup++) {
1320 pup_num = (pup == dram_info->num_of_std_pups) ? ECC_BIT : pup;
1321 phase = dram_info->wl_val[cs][pup][P];
1322 delay = dram_info->wl_val[cs][pup][D];
1336 * Perform DDR3 Control PUP Indirect Write
1338 static void ddr3_write_ctrl_pup_reg(int bc_acc, u32 pup, u32 reg_addr, u32 data)
1352 reg |= (pup << REG_PHY_PUP_OFFS);
