Lines Matching refs:ret_val
425 int32_t ret_val = E1000_SUCCESS;
573 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
575 if (ret_val)
576 return ret_val;
593 return ret_val;
884 int32_t ret_val = 0;
892 ret_val = -E1000_ERR_EEPROM;
906 ret_val = 0;
912 if (ret_val) {
919 return ret_val;
929 int32_t ret_val = -E1000_ERR_EEPROM;
935 ret_val = 0;
941 return ret_val;
951 int32_t ret_val = 0;
954 ret_val = e1000_pool_flash_update_done_i210(hw);
955 if (ret_val == -E1000_ERR_EEPROM) {
963 ret_val = e1000_pool_flash_update_done_i210(hw);
964 if (ret_val)
970 return ret_val;
983 int32_t ret_val = 0;
991 ret_val = e1000_read_eeprom_eerd(hw, 0, 1, &nvm_data);
992 if (ret_val) {
1004 ret_val = e1000_read_eeprom_eerd(hw, i, 1, &nvm_data);
1005 if (ret_val) {
1013 ret_val = e1000_write_eeprom_srwr(hw, EEPROM_CHECKSUM_REG, 1,
1015 if (ret_val) {
1023 ret_val = e1000_update_flash_i210(hw);
1025 ret_val = -E1000_ERR_SWFW_SYNC;
1029 return ret_val;
1093 int32_t ret_val;
1100 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
1102 if (ret_val)
1103 return ret_val;
1107 ret_val = e1000_write_phy_reg(hw,
1109 if (ret_val)
1110 return ret_val;
1111 ret_val = e1000_write_phy_reg(hw,
1113 if (ret_val)
1114 return ret_val;
1384 int ret_val;
1388 ret_val = e1000_read_mac_addr_from_regs(hw, enetaddr);
1390 ret_val = e1000_read_mac_addr_from_eeprom(hw, enetaddr);
1392 if (ret_val)
1393 return ret_val;
1846 int32_t ret_val;
1977 ret_val = e1000_setup_link(hw);
2048 return ret_val;
2065 int32_t ret_val;
2103 ret_val = e1000_read_eeprom(hw,
2105 if (ret_val) {
2151 ret_val = (hw->media_type == e1000_media_type_fiber) ?
2153 if (ret_val < 0) {
2154 return ret_val;
2196 return ret_val;
2216 int32_t ret_val;
2317 ret_val = e1000_check_for_link(hw);
2318 if (ret_val < 0) {
2320 return ret_val;
2343 int32_t ret_val;
2361 ret_val = e1000_phy_hw_reset(hw);
2362 if (ret_val)
2363 return ret_val;
2367 ret_val = e1000_detect_gig_phy(hw);
2368 if (ret_val) {
2370 return ret_val;
2375 ret_val = e1000_set_phy_mode(hw);
2376 if (ret_val)
2377 return ret_val;
2380 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2383 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2414 int32_t ret_val;
2427 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2429 if (ret_val)
2430 return ret_val;
2437 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2439 if (ret_val)
2440 return ret_val;
2447 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2449 if (ret_val)
2450 return ret_val;
2457 ret_val = e1000_write_phy_reg(hw,
2459 if (ret_val)
2460 return ret_val;
2469 ret_val = e1000_read_phy_reg(hw,
2471 if (ret_val)
2472 return ret_val;
2475 ret_val = e1000_write_phy_reg(hw,
2477 if (ret_val)
2478 return ret_val;
2480 ret_val = e1000_read_phy_reg(hw,
2482 if (ret_val)
2483 return ret_val;
2486 ret_val = e1000_write_phy_reg(hw,
2488 if (ret_val)
2489 return ret_val;
2499 ret_val = e1000_write_phy_reg(hw,
2501 if (ret_val)
2502 return ret_val;
2509 ret_val = e1000_write_phy_reg(hw,
2511 if (ret_val)
2512 return ret_val;
2517 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2519 if (ret_val)
2520 return ret_val;
2523 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2525 if (ret_val)
2526 return ret_val;
2549 int32_t ret_val;
2561 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2563 if (ret_val)
2564 return ret_val;
2576 ret_val = e1000_write_phy_reg(hw,
2578 if (ret_val)
2579 return ret_val;
2590 ret_val = e1000_read_phy_reg(hw,
2592 if (ret_val)
2593 return ret_val;
2596 ret_val = e1000_write_phy_reg(hw,
2598 if (ret_val)
2599 return ret_val;
2601 ret_val = e1000_read_phy_reg(hw,
2603 if (ret_val)
2604 return ret_val;
2607 ret_val = e1000_write_phy_reg(hw,
2609 if (ret_val)
2610 return ret_val;
2624 ret_val = e1000_write_phy_reg(hw,
2626 if (ret_val)
2627 return ret_val;
2634 ret_val = e1000_read_phy_reg(hw,
2636 if (ret_val)
2637 return ret_val;
2640 ret_val = e1000_write_phy_reg(hw,
2642 if (ret_val)
2643 return ret_val;
2658 int32_t ret_val;
2666 ret_val = e1000_phy_reset(hw);
2667 if (ret_val) {
2669 return ret_val;
2685 ret_val = e1000_set_d3_lplu_state(hw, false);
2686 if (ret_val) {
2688 return ret_val;
2693 ret_val = e1000_set_d0_lplu_state(hw, false);
2694 if (ret_val) {
2696 return ret_val;
2699 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2700 if (ret_val)
2701 return ret_val;
2727 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2728 if (ret_val)
2729 return ret_val;
2746 ret_val = e1000_read_phy_reg(hw,
2748 if (ret_val)
2749 return ret_val;
2751 ret_val = e1000_write_phy_reg(hw,
2753 if (ret_val)
2754 return ret_val;
2756 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2758 if (ret_val)
2759 return ret_val;
2761 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2763 if (ret_val)
2764 return ret_val;
2767 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2768 if (ret_val)
2769 return ret_val;
2791 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2792 if (ret_val)
2793 return ret_val;
2880 int32_t ret_val;
2888 ret_val = e1000_read_phy_reg(hw,
2890 if (ret_val)
2891 return ret_val;
2897 ret_val = e1000_write_phy_reg(hw,
2899 if (ret_val)
2900 return ret_val;
2909 ret_val = e1000_read_phy_reg(hw,
2911 if (ret_val)
2912 return ret_val;
2936 ret_val = e1000_write_phy_reg(hw,
2939 if (ret_val)
2940 return ret_val;
2943 ret_val = e1000_phy_reset(hw);
2944 if (ret_val) {
2946 return ret_val;
2952 ret_val = e1000_write_kmrn_reg(hw,
2956 if (ret_val)
2957 return ret_val;
2959 ret_val = e1000_read_phy_reg(hw,
2961 if (ret_val)
2962 return ret_val;
2965 ret_val = e1000_write_phy_reg(hw,
2968 if (ret_val)
2969 return ret_val;
2975 ret_val = e1000_read_phy_reg(hw,
2977 if (ret_val)
2978 return ret_val;
2987 ret_val = e1000_write_phy_reg(hw,
2989 if (ret_val)
2990 return ret_val;
2992 ret_val = e1000_read_phy_reg(hw,
2994 if (ret_val)
2995 return ret_val;
2998 ret_val = e1000_write_phy_reg(hw,
3001 if (ret_val)
3002 return ret_val;
3008 ret_val = e1000_read_phy_reg(hw,
3010 if (ret_val)
3011 return ret_val;
3013 ret_val = e1000_write_phy_reg(hw,
3015 if (ret_val)
3016 return ret_val;
3029 int32_t ret_val;
3038 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
3039 if (ret_val)
3040 return ret_val;
3076 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
3077 if (ret_val)
3078 return ret_val;
3084 ret_val = e1000_read_phy_reg(hw,
3086 if (ret_val)
3087 return ret_val;
3096 ret_val = e1000_write_phy_reg(hw,
3098 if (ret_val)
3099 return ret_val;
3106 ret_val = e1000_write_phy_reg(hw,
3108 if (ret_val)
3109 return ret_val;
3114 ret_val = e1000_phy_reset(hw);
3115 if (ret_val) {
3117 return ret_val;
3132 int32_t ret_val;
3153 ret_val = e1000_phy_setup_autoneg(hw);
3154 if (ret_val) {
3156 return ret_val;
3163 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3164 if (ret_val)
3165 return ret_val;
3168 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3169 if (ret_val)
3170 return ret_val;
3180 ret_val = e1000_wait_autoneg(hw);
3181 if (ret_val) {
3184 return ret_val;
3208 int32_t ret_val;
3214 ret_val = e1000_config_mac_to_phy(hw);
3215 if (ret_val) {
3217 return ret_val;
3220 ret_val = e1000_config_fc_after_link_up(hw);
3221 if (ret_val) {
3223 return ret_val;
3236 int32_t ret_val;
3249 ret_val = e1000_write_kmrn_reg(hw,
3251 if (ret_val)
3252 return ret_val;
3253 ret_val = e1000_read_kmrn_reg(hw,
3255 if (ret_val)
3256 return ret_val;
3258 ret_val = e1000_write_kmrn_reg(hw,
3260 if (ret_val)
3261 return ret_val;
3267 ret_val = e1000_copper_link_preconfig(hw);
3268 if (ret_val)
3269 return ret_val;
3276 ret_val = e1000_write_kmrn_reg(hw,
3278 if (ret_val)
3279 return ret_val;
3288 ret_val = e1000_copper_link_igp_setup(hw);
3289 if (ret_val)
3290 return ret_val;
3293 ret_val = e1000_copper_link_mgp_setup(hw);
3294 if (ret_val)
3295 return ret_val;
3297 ret_val = e1000_copper_link_ggp_setup(hw);
3298 if (ret_val)
3299 return ret_val;
3305 ret_val = e1000_copper_link_autoneg(hw);
3306 if (ret_val)
3307 return ret_val;
3313 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3314 if (ret_val)
3315 return ret_val;
3316 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3317 if (ret_val)
3318 return ret_val;
3322 ret_val = e1000_copper_link_postconfig(hw);
3323 if (ret_val)
3324 return ret_val;
3344 int32_t ret_val;
3351 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3352 if (ret_val)
3353 return ret_val;
3357 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3359 if (ret_val)
3360 return ret_val;
3469 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3470 if (ret_val)
3471 return ret_val;
3476 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3478 if (ret_val)
3479 return ret_val;
3646 int32_t ret_val;
3664 ret_val = e1000_force_mac_fc(hw);
3665 if (ret_val < 0) {
3667 return ret_val;
3836 ret_val = e1000_force_mac_fc(hw);
3837 if (ret_val < 0) {
3840 return ret_val;
3865 int32_t ret_val;
3924 ret_val = e1000_config_mac_to_phy(hw);
3925 if (ret_val < 0) {
3928 return ret_val;
3936 ret_val = e1000_config_fc_after_link_up(hw);
3937 if (ret_val < 0) {
3939 return ret_val;
4013 ret_val = e1000_config_fc_after_link_up(hw);
4014 if (ret_val < 0) {
4016 return ret_val;
4042 int32_t ret_val = E1000_SUCCESS;
4049 ret_val = e1000_write_kmrn_reg(hw,
4051 if (ret_val)
4052 return ret_val;
4060 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
4062 if (ret_val)
4063 return ret_val;
4070 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
4072 return ret_val;
4078 int32_t ret_val = E1000_SUCCESS;
4085 ret_val = e1000_write_kmrn_reg(hw,
4087 if (ret_val)
4088 return ret_val;
4096 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
4098 if (ret_val)
4099 return ret_val;
4102 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
4104 return ret_val;
4119 int32_t ret_val;
4155 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
4156 if (ret_val)
4157 return ret_val;
4162 ret_val = e1000_read_phy_reg(hw,
4164 if (ret_val)
4165 return ret_val;
4177 ret_val = e1000_configure_kmrn_for_1000(hw);
4179 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
4180 if (ret_val)
4181 return ret_val;
4596 int32_t ret_val;
4602 ret_val = e1000_check_phy_reset_block(hw);
4603 if (ret_val)
4662 ret_val = e1000_get_phy_cfg_done(hw);
4663 if (ret_val != E1000_SUCCESS)
4664 return ret_val;
4666 return ret_val;
4677 uint32_t ret_val;
4686 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4732 if (!ret_val)
4786 int32_t ret_val;
4793 ret_val = e1000_check_phy_reset_block(hw);
4794 if (ret_val)
4803 ret_val = e1000_phy_hw_reset(hw);
4804 if (ret_val)
4805 return ret_val;
4808 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4809 if (ret_val)
4810 return ret_val;
4813 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4814 if (ret_val)
4815 return ret_val;
4886 int32_t phy_init_status, ret_val;
4912 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4913 if (ret_val)
4914 return ret_val;
4918 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4919 if (ret_val)
4920 return ret_val;
5441 int ret_val = 0;
5443 ret_val = e1000_reset(hw, enetaddr);
5444 if (ret_val < 0) {
5445 if ((ret_val == -E1000_ERR_NOLINK) ||
5446 (ret_val == -E1000_ERR_TIMEOUT)) {
5447 E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val);
5451 return ret_val;
5659 int ret_val, i;
5668 ret_val = e1000_read_mac_addr_from_eeprom(hw, current_mac);
5674 if (!ret_val && memcmp(current_mac, mac, 6) == 0)
5680 ret_val = e1000_write_eeprom_srwr(hw, 0x0, 3, data);
5682 if (!ret_val)
5683 ret_val = e1000_update_eeprom_checksum_i210(hw);
5685 return ret_val;
