Lines Matching refs:rxq
92 #define MVPP2_RXQ_CONFIG_REG(rxq) (0x800 + 4 * (rxq))
151 #define MVPP2_RXQ_STATUS_UPDATE_REG(rxq) (0x3000 + 4 * (rxq))
154 #define MVPP2_RXQ_STATUS_REG(rxq) (0x3400 + 4 * (rxq))
232 #define MVPP2_ISR_RX_THRESHOLD_REG(rxq) (0x5200 + 4 * (rxq))
233 #define MVPP21_ISR_RXQ_GROUP_REG(rxq) (0x5400 + 4 * (rxq))
1007 /* Index of first port's physical RXQ */
1187 /* ID of port to which physical RXQ is mapped */
1190 /* Port's logic RXQ number to which physical RXQ is mapped */
2712 /* Attach long pool to rxq */
2870 int rxq;
2882 for (rxq = 0; rxq < rxq_number; rxq++)
2883 mvpp2_rxq_long_pool_set(port, rxq, port->pool_long->id);
3878 mvpp2_rxq_next_desc_get(struct mvpp2_rx_queue *rxq)
3880 int rx_desc = rxq->next_desc_to_proc;
3882 rxq->next_desc_to_proc = MVPP2_QUEUE_NEXT_DESC(rxq, rx_desc);
3883 prefetch(rxq->descs + rxq->next_desc_to_proc);
3884 return rxq->descs + rx_desc;
4099 struct mvpp2_rx_queue *rxq)
4104 rxq->size = port->rx_ring_size;
4107 rxq->descs = buffer_loc.rx_descs;
4108 rxq->descs_dma = (dma_addr_t)buffer_loc.rx_descs;
4109 if (!rxq->descs)
4112 BUG_ON(rxq->descs !=
4113 PTR_ALIGN(rxq->descs, MVPP2_CPU_D_CACHE_LINE_SIZE));
4115 rxq->last_desc = rxq->size - 1;
4118 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4121 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4123 rxq_dma = rxq->descs_dma;
4125 rxq_dma = rxq->descs_dma >> MVPP22_DESC_ADDR_OFFS;
4127 mvpp2_write(port->priv, MVPP2_RXQ_DESC_SIZE_REG, rxq->size);
4131 mvpp2_rxq_offset_set(port, rxq->id, NET_SKB_PAD);
4134 mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
4139 /* Push packets received by the RXQ to BM pool */
4141 struct mvpp2_rx_queue *rxq)
4145 rx_received = mvpp2_rxq_received(port, rxq->id);
4150 struct mvpp2_rx_desc *rx_desc = mvpp2_rxq_next_desc_get(rxq);
4157 mvpp2_rxq_status_update(port, rxq->id, rx_received, rx_received);
4162 struct mvpp2_rx_queue *rxq)
4164 mvpp2_rxq_drop_pkts(port, rxq);
4166 rxq->descs = NULL;
4167 rxq->last_desc = 0;
4168 rxq->next_desc_to_proc = 0;
4169 rxq->descs_dma = 0;
4174 mvpp2_write(port->priv, MVPP2_RXQ_STATUS_REG(rxq->id), 0);
4175 mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
4673 struct mvpp2_rx_queue *rxq;
4676 rxq = devm_kzalloc(dev, sizeof(*rxq), GFP_KERNEL);
4677 if (!rxq)
4680 rxq->id = port->first_rxq + queue;
4681 rxq->port = port->id;
4682 rxq->logic_rxq = queue;
4684 port->rxqs[queue] = rxq;
4690 struct mvpp2_rx_queue *rxq = port->rxqs[queue];
4692 rxq->size = port->rx_ring_size;
4693 rxq->pkts_coal = MVPP2_RX_COAL_PKTS;
4694 rxq->time_coal = MVPP2_RX_COAL_USEC;
4999 /* Checks for hardware constraints (U-Boot uses only one rxq) */
5194 struct mvpp2_rx_queue *rxq;
5198 rxq = port->rxqs[0];
5201 rx_received = mvpp2_rxq_received(port, rxq->id);
5207 rx_desc = mvpp2_rxq_next_desc_get(rxq);
5237 mvpp2_rxq_status_update(port, rxq->id, 1, 1);
