Lines Matching refs:tcwl
155 u32 tcl, u32 tal, u32 tcwl)
165 clrsetbits_le32(&phy->reg[0xc], 0x0f, tcwl);
241 mr[2] = DDR3_MR2_TWL(params->pctl_timing.tcwl);
473 pctl_timing->tcwl = 10;
476 pctl_timing->tcwl = 6;
479 pctl_timing->tcwl = 7;
482 pctl_timing->tcwl = 8;
493 pctl_timing->trtw = pctl_timing->tcl + tccd/2 + 2 - pctl_timing->tcwl;
560 writel((params->pctl_timing.tcwl - 1) / 2 - 1, &pctl->dfitphywrlat);
832 params->pctl_timing.tcwl);