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Lines Matching refs:u1u2

1827 		reg |= dwc->u1u2;
1830 		dwc->u1u2 = 0;
2307 			u32	u1u2;
2314 				u1u2 = reg & (DWC3_DCTL_INITU2ENA
2319 				if (!dwc->u1u2)
2320 					dwc->u1u2 = reg & u1u2;
2322 				reg &= ~u1u2;