Lines Matching refs:regs
51 struct fotg210_regs *regs;
79 struct fotg210_regs *regs = chip->regs;
83 setbits_le32(®s->iep[ep - 1], IEP_RESET);
85 clrbits_le32(®s->iep[ep - 1], IEP_RESET);
87 clrbits_le32(®s->iep[ep - 1], IEP_STALL);
90 setbits_le32(®s->oep[ep - 1], OEP_RESET);
92 clrbits_le32(®s->oep[ep - 1], OEP_RESET);
94 clrbits_le32(®s->oep[ep - 1], OEP_STALL);
102 struct fotg210_regs *regs = chip->regs;
108 writel(DEVCTRL_EN, ®s->dev_ctrl);
112 writel(0, ®s->dev_addr);
115 writel(7, ®s->idle);
118 writel(IMR_MASK, ®s->imr);
119 writel(GIMR_MASK, ®s->gimr);
120 writel(GIMR0_MASK, ®s->gimr0);
121 writel(GIMR1_MASK, ®s->gimr1);
122 writel(GIMR2_MASK, ®s->gimr2);
125 writel(ISR_MASK, ®s->isr);
126 writel(0, ®s->gisr);
127 writel(0, ®s->gisr0);
128 writel(0, ®s->gisr1);
129 writel(0, ®s->gisr2);
132 setbits_le32(®s->dev_ctrl, DEVCTRL_RESET);
134 if (readl(®s->dev_ctrl) & DEVCTRL_RESET) {
140 setbits_le32(®s->cxfifo, CXFIFO_CXFIFOCLR);
142 if (readl(®s->cxfifo) & CXFIFO_CXFIFOCLR) {
148 writel(EPMAP14_DEFAULT, ®s->epmap14);
149 writel(EPMAP58_DEFAULT, ®s->epmap58);
150 writel(FIFOMAP_DEFAULT, ®s->fifomap);
151 writel(0, ®s->fifocfg);
153 writel(CFG_EPX_MAX_PACKET_SIZE, ®s->iep[i]);
154 writel(CFG_EPX_MAX_PACKET_SIZE, ®s->oep[i]);
159 writel(FIFOCSR_RESET, ®s->fifocsr[i]);
161 if (readl(®s->fifocsr[i]) & FIFOCSR_RESET) {
168 writel(IMR_IRQLH | IMR_HOST | IMR_OTG, ®s->imr);
169 writel(ISR_MASK, ®s->isr);
171 writel(GIMR0_CXOUT | GIMR0_CXIN, ®s->gimr0);
173 writel(GIMR1_MASK, ®s->gimr1);
176 | GIMR2_ZLPRX | GIMR2_ZLPTX, ®s->gimr2);
178 writel(0, ®s->gimr);
181 writel(3, ®s->idle);
184 setbits_le32(®s->dev_ctrl, DEVCTRL_GIRQ_EN);
191 struct fotg210_regs *regs = chip->regs;
196 if ((readl(®s->cxfifo) & mask) != mask)
211 struct fotg210_regs *regs = chip->regs;
224 if (!(readl(®s->dma_ctrl) & DMACTRL_START)) {
241 writel(virt_to_phys(buf), ®s->dma_addr);
248 writel(DMAFIFO_CX, ®s->dma_fifo);
252 writel(DMAFIFO_FIFO(fifo), ®s->dma_fifo);
254 writel(DMACTRL_LEN(len) | DMACTRL_MEM2FIFO, ®s->dma_ctrl);
259 writel(DMAFIFO_CX, ®s->dma_fifo);
261 blen = CXFIFO_BYTES(readl(®s->cxfifo));
264 writel(DMAFIFO_FIFO(fifo), ®s->dma_fifo);
265 blen = FIFOCSR_BYTES(readl(®s->fifocsr[fifo]));
268 writel(DMACTRL_LEN(len) | DMACTRL_FIFO2MEM, ®s->dma_ctrl);
272 setbits_le32(®s->dma_ctrl, DMACTRL_START);
277 tmp = readl(®s->gisr2);
297 writel(DMACTRL_ABORT | DMACTRL_CLRFF, ®s->dma_ctrl);
299 writel(0, ®s->gisr2);
300 writel(0, ®s->dma_fifo);
323 struct fotg210_regs *regs = chip->regs;
331 if (readl(®s->otgcsr) & OTGCSR_DEV_B) {
333 if (readl(®s->dev_ctrl) & DEVCTRL_HS) {
337 writel(SOFMTR_TMR(1100), ®s->sof_mtr);
342 writel(SOFMTR_TMR(10000), ®s->sof_mtr);
350 writel(DMAFIFO_CX, ®s->dma_fifo);
352 tmp[0] = readl(®s->ep0_data);
353 tmp[1] = readl(®s->ep0_data);
355 writel(0, ®s->dma_fifo);
370 writel(chip->addr, ®s->dev_addr);
374 ®s->dev_addr);
384 writel(chip->addr, ®s->dev_addr);
409 setbits_le32(®s->iep[id - 1], IEP_STALL);
410 setbits_le32(®s->oep[id - 1], OEP_STALL);
447 setbits_le32(®s->cxfifo, CXFIFO_CXFIN);
451 setbits_le32(®s->cxfifo, CXFIFO_CXSTALL | CXFIFO_CXFIN);
468 struct fotg210_regs *regs = chip->regs;
492 setbits_le32(®s->gimr1,
505 struct fotg210_regs *regs = chip->regs;
520 setbits_le32(®s->fifomap, FIFOMAP(id, FIFOMAP_IN));
527 setbits_le32(®s->fifocfg,
532 setbits_le32(®s->fifocfg,
537 setbits_le32(®s->fifocfg,
549 struct fotg210_regs *regs = chip->regs;
555 clrbits_le32(®s->fifocfg, FIFOCFG(id, FIFOCFG_CFG_MASK));
556 clrbits_le32(®s->fifomap, FIFOMAP(id, FIFOMAP_DIR_MASK));
587 struct fotg210_regs *regs = chip->regs;
629 clrbits_le32(®s->gimr1,
672 struct fotg210_regs *regs = chip->regs;
684 setbits_le32(®s->iep[ep->id - 1],
687 setbits_le32(®s->oep[ep->id - 1],
692 clrbits_le32(®s->iep[ep->id - 1],
695 clrbits_le32(®s->oep[ep->id - 1],
710 struct fotg210_regs *regs = chip->regs;
717 setbits_le32(®s->dev_ctrl, DEVCTRL_EN);
719 clrbits_le32(®s->phy_tmsr, PHYTMSR_UNPLUG);
725 writel(chip->addr, ®s->dev_addr);
727 setbits_le32(®s->phy_tmsr, PHYTMSR_UNPLUG);
729 clrbits_le32(®s->dev_ctrl, DEVCTRL_EN);
749 struct fotg210_regs *regs;
752 regs = chip->regs;
754 return SOFFNR_FNR(readl(®s->sof_fnr));
773 .regs = (void __iomem *)CONFIG_FOTG210_BASE,
837 struct fotg210_regs *regs = chip->regs;
840 isr = readl(®s->isr) & (~readl(®s->imr));
841 gisr = readl(®s->gisr) & (~readl(®s->gimr));
845 writel(ISR_DEV, ®s->isr);
849 st = readl(®s->gisr0);
856 writel(st & GISR0_CXABORT, ®s->gisr0);
857 writel(0, ®s->gisr0);
868 setbits_le32(®s->cxfifo, CXFIFO_CXFIN);
873 st = readl(®s->gisr1);
882 st = readl(®s->gisr2);
889 writel(st, ®s->gisr2);
890 writel(0, ®s->gisr2);
