Lines Matching refs:ddr_clk
206 u64 ddr_clk = priv->phy_clk;
233 test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3;
244 if (ddr_clk / (MHz) >= freq_rang[i][0])
258 * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz
274 if ((ddr_clk * i % refclk < remain) &&
275 (ddr_clk * i / refclk) < max_fbdiv) {
277 remain = ddr_clk * i % refclk;
280 fbdiv = ddr_clk * prediv / refclk;
281 ddr_clk = refclk * fbdiv / prediv;
282 priv->phy_clk = ddr_clk;
285 __func__, refclk, prediv, fbdiv, ddr_clk);
