Lines Matching refs:refclk
207 u32 refclk = priv->ref_clk;
208 u32 remain = refclk;
258 * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz
261 max_prediv = (refclk / (5 * MHz));
262 min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1);
268 debug("%s: Invalid refclk value\n", __func__);
272 /* Calculate the best refclk and feedback division value for dphy pll */
274 if ((ddr_clk * i % refclk < remain) &&
275 (ddr_clk * i / refclk) < max_fbdiv) {
277 remain = ddr_clk * i % refclk;
280 fbdiv = ddr_clk * prediv / refclk;
281 ddr_clk = refclk * fbdiv / prediv;
284 debug("%s: DEBUG: refclk=%u, refclk=%llu, fbdiv=%llu, phyclk=%llu\n",
285 __func__, refclk, prediv, fbdiv, ddr_clk);
