Lines Matching refs:timing
29 struct display_timing *timing)
34 0, timing);
36 debug("%s: Failed to decode display timing (ret=%d)\n",
79 const struct display_timing *timing)
90 /* Set Display timing parameter */
91 rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ);
92 rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ);
93 rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ
94 + timing->hback_porch.typ + timing->hactive.typ
95 + timing->hfront_porch.typ));
96 rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ);
97 rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ);
98 rk_mipi_dsi_write(regs, VID_VFP_LINES, timing->vfront_porch.typ);
99 rk_mipi_dsi_write(regs, VID_ACTIVE_LINES, timing->vactive.typ);
102 val = (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) ? 1 : 0;
105 val = (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) ? 1 : 0;
108 val = (timing->flags & DISPLAY_FLAGS_DE_LOW) ? 1 : 0;
111 val = (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) ? 1 : 0;
158 /* Phy State transfer timing */
