Lines Matching defs:Address
44 typedef void *Address ;
187 * Controller (UDC) Address Register (read/write).
216 #define _Ser0UDCAR 0x80000004 /* Ser. port 0 UDC Address Reg. */
237 #define Ser0UDCAR /* Ser. port 0 UDC Address Reg. */ \
280 #define UDCAR_ADD Fld (7, 0) /* function ADDress */
701 #define SDCR1_AME 0x00000020 /* Address Match Enable */
707 #define SDCR2_AMV Fld (8, 0) /* Address Match Value */
811 #define HSCR0_AME 0x00000080 /* Address Match Enable */
813 #define HSCR1_AMV Fld (8, 0) /* Address Match Value */
965 #define MCDR2_ADD Fld (4, 17) /* reg. ADDress */
1799 * Column Address Strobe (CAS) shift register 0
1802 * Column Address Strobe (CAS) shift register 1
1805 * Column Address Strobe (CAS) shift register 2
1845 #define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */
1846 Address count [9..12] */ \
2067 * DDAR0 Direct Memory Access (DMA) Device Address Register
2071 * DBSA0 Direct Memory Access (DMA) Buffer Start address
2075 * DBSB0 Direct Memory Access (DMA) Buffer Start address
2080 * DDAR1 Direct Memory Access (DMA) Device Address Register
2084 * DBSA1 Direct Memory Access (DMA) Buffer Start address
2088 * DBSB1 Direct Memory Access (DMA) Buffer Start address
2093 * DDAR2 Direct Memory Access (DMA) Device Address Register
2097 * DBSA2 Direct Memory Access (DMA) Buffer Start address
2101 * DBSB2 Direct Memory Access (DMA) Buffer Start address
2106 * DDAR3 Direct Memory Access (DMA) Device Address Register
2110 * DBSA3 Direct Memory Access (DMA) Buffer Start address
2114 * DBSB3 Direct Memory Access (DMA) Buffer Start address
2119 * DDAR4 Direct Memory Access (DMA) Device Address Register
2123 * DBSA4 Direct Memory Access (DMA) Buffer Start address
2127 * DBSB4 Direct Memory Access (DMA) Buffer Start address
2132 * DDAR5 Direct Memory Access (DMA) Device Address Register
2136 * DBSA5 Direct Memory Access (DMA) Buffer Start address
2140 * DBSB5 Direct Memory Access (DMA) Buffer Start address
2148 #define _DDAR(Nb) /* DMA Device Address Reg. */ \
2160 #define _DBSA(Nb) /* DMA Buffer Start address reg. A */ \
2166 #define _DBSB(Nb) /* DMA Buffer Start address reg. B */ \
2173 #define _DDAR0 _DDAR (0) /* DMA Device Address Reg. */
2181 #define _DBSA0 _DBSA (0) /* DMA Buffer Start address reg. A */
2185 #define _DBSB0 _DBSB (0) /* DMA Buffer Start address reg. B */
2190 #define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */
2198 #define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */
2202 #define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */
2207 #define _DDAR2 _DDAR (2) /* DMA Device Address Reg. */
2215 #define _DBSA2 _DBSA (2) /* DMA Buffer Start address reg. A */
2219 #define _DBSB2 _DBSB (2) /* DMA Buffer Start address reg. B */
2224 #define _DDAR3 _DDAR (3) /* DMA Device Address Reg. */
2232 #define _DBSA3 _DBSA (3) /* DMA Buffer Start address reg. A */
2236 address reg. B */
2241 #define _DDAR4 _DDAR (4) /* DMA Device Address Reg. */
2249 #define _DBSA4 _DBSA (4) /* DMA Buffer Start address reg. A */
2253 #define _DBSB4 _DBSB (4) /* DMA Buffer Start address reg. B */
2258 #define _DDAR5 _DDAR (5) /* DMA Device Address Reg. */
2266 #define _DBSA5 _DBSA (5) /* DMA Buffer Start address reg. A */
2270 #define _DBSB5 _DBSB (5) /* DMA Buffer Start address reg. B */
2277 #define DDAR0 /* DMA Device Address Reg. */ \
2289 #define DBSA0 /* DMA Buffer Start address reg. A */ \
2291 (*((volatile Address *) io_p2v (_DBSA0)))
2295 #define DBSB0 /* DMA Buffer Start address reg. B */ \
2297 (*((volatile Address *) io_p2v (_DBSB0)))
2302 #define DDAR1 /* DMA Device Address Reg. */ \
2314 #define DBSA1 /* DMA Buffer Start address reg. A */ \
2316 (*((volatile Address *) io_p2v (_DBSA1)))
2320 #define DBSB1 /* DMA Buffer Start address reg. B */ \
2322 (*((volatile Address *) io_p2v (_DBSB1)))
2327 #define DDAR2 /* DMA Device Address Reg. */ \
2339 #define DBSA2 /* DMA Buffer Start address reg. A */ \
2341 (*((volatile Address *) io_p2v (_DBSA2)))
2345 #define DBSB2 /* DMA Buffer Start address reg. B */ \
2347 (*((volatile Address *) io_p2v (_DBSB2)))
2352 #define DDAR3 /* DMA Device Address Reg. */ \
2364 #define DBSA3 /* DMA Buffer Start address reg. A */ \
2366 (*((volatile Address *) io_p2v (_DBSA3)))
2370 #define DBSB3 /* DMA Buffer Start address reg. B */ \
2372 (*((volatile Address *) io_p2v (_DBSB3)))
2377 #define DDAR4 /* DMA Device Address Reg. */ \
2389 #define DBSA4 /* DMA Buffer Start address reg. A */ \
2391 (*((volatile Address *) io_p2v (_DBSA4)))
2395 #define DBSB4 /* DMA Buffer Start address reg. B */ \
2397 (*((volatile Address *) io_p2v (_DBSB4)))
2402 #define DDAR5 /* DMA Device Address Reg. */ \
2414 #define DBSA5 /* DMA Buffer Start address reg. A */ \
2416 (*((volatile Address *) io_p2v (_DBSA5)))
2420 #define DBSB5 /* DMA Buffer Start address reg. B */ \
2422 (*((volatile Address *) io_p2v (_DBSB5)))
2480 #define DDAR_DA Fld (24, 8) /* Device Address */
2481 #define DDAR_DevAdd(Add) /* Device Address */ \
2573 * (DMA) Base Address Register channel 1 (read/write).
2575 * (DMA) Current Address Register channel 1 (read).
2577 * (DMA) Base Address Register channel 2 (read/write).
2579 * (DMA) Current Address Register channel 2 (read).
2652 #define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */
2654 #define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */
2656 #define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */
2658 #define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */
2669 #define DBAR1 /* LCD DMA Base Address Reg. */ \
2671 (*((volatile Address *) io_p2v (_DBAR1)))
2672 #define DCAR1 /* LCD DMA Current Address Reg. */ \
2674 (*((volatile Address *) io_p2v (_DCAR1)))
2675 #define DBAR2 /* LCD DMA Base Address Reg. */ \
2677 (*((volatile Address *) io_p2v (_DBAR2)))
2678 #define DCAR2 /* LCD DMA Current Address Reg. */ \
2680 (*((volatile Address *) io_p2v (_DCAR2)))
2699 #define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */
2723 #define LCSR_BAU 0x00000002 /* Base Address Update (read) */
