Lines Matching refs:src2
1483 void Assembler::and_(Register dst, Register src1, const Operand& src2,
1485 AddrMode1(cond | AND | s, dst, src1, src2);
1488 void Assembler::and_(Register dst, Register src1, Register src2, SBit s,
1490 and_(dst, src1, Operand(src2), s, cond);
1493 void Assembler::eor(Register dst, Register src1, const Operand& src2,
1495 AddrMode1(cond | EOR | s, dst, src1, src2);
1499 void Assembler::sub(Register dst, Register src1, const Operand& src2,
1501 AddrMode1(cond | SUB | s, dst, src1, src2);
1504 void Assembler::sub(Register dst, Register src1, Register src2, SBit s,
1506 sub(dst, src1, Operand(src2), s, cond);
1509 void Assembler::rsb(Register dst, Register src1, const Operand& src2,
1511 AddrMode1(cond | RSB | s, dst, src1, src2);
1515 void Assembler::add(Register dst, Register src1, const Operand& src2,
1517 AddrMode1(cond | ADD | s, dst, src1, src2);
1520 void Assembler::add(Register dst, Register src1, Register src2, SBit s,
1522 add(dst, src1, Operand(src2), s, cond);
1525 void Assembler::adc(Register dst, Register src1, const Operand& src2,
1527 AddrMode1(cond | ADC | s, dst, src1, src2);
1531 void Assembler::sbc(Register dst, Register src1, const Operand& src2,
1533 AddrMode1(cond | SBC | s, dst, src1, src2);
1537 void Assembler::rsc(Register dst, Register src1, const Operand& src2,
1539 AddrMode1(cond | RSC | s, dst, src1, src2);
1543 void Assembler::tst(Register src1, const Operand& src2, Condition cond) {
1544 AddrMode1(cond | TST | S, no_reg, src1, src2);
1547 void Assembler::tst(Register src1, Register src2, Condition cond) {
1548 tst(src1, Operand(src2), cond);
1551 void Assembler::teq(Register src1, const Operand& src2, Condition cond) {
1552 AddrMode1(cond | TEQ | S, no_reg, src1, src2);
1556 void Assembler::cmp(Register src1, const Operand& src2, Condition cond) {
1557 AddrMode1(cond | CMP | S, no_reg, src1, src2);
1560 void Assembler::cmp(Register src1, Register src2, Condition cond) {
1561 cmp(src1, Operand(src2), cond);
1571 void Assembler::cmn(Register src1, const Operand& src2, Condition cond) {
1572 AddrMode1(cond | CMN | S, no_reg, src1, src2);
1576 void Assembler::orr(Register dst, Register src1, const Operand& src2,
1578 AddrMode1(cond | ORR | s, dst, src1, src2);
1581 void Assembler::orr(Register dst, Register src1, Register src2, SBit s,
1583 orr(dst, src1, Operand(src2), s, cond);
1648 void Assembler::bic(Register dst, Register src1, const Operand& src2,
1650 AddrMode1(cond | BIC | s, dst, src1, src2);
1658 void Assembler::asr(Register dst, Register src1, const Operand& src2, SBit s,
1660 if (src2.IsRegister()) {
1661 mov(dst, Operand(src1, ASR, src2.rm()), s, cond);
1663 mov(dst, Operand(src1, ASR, src2.immediate()), s, cond);
1667 void Assembler::lsl(Register dst, Register src1, const Operand& src2, SBit s,
1669 if (src2.IsRegister()) {
1670 mov(dst, Operand(src1, LSL, src2.rm()), s, cond);
1672 mov(dst, Operand(src1, LSL, src2.immediate()), s, cond);
1676 void Assembler::lsr(Register dst, Register src1, const Operand& src2, SBit s,
1678 if (src2.IsRegister()) {
1679 mov(dst, Operand(src1, LSR, src2.rm()), s, cond);
1681 mov(dst, Operand(src1, LSR, src2.immediate()), s, cond);
1686 void Assembler::mla(Register dst, Register src1, Register src2, Register srcA,
1688 DCHECK(dst != pc && src1 != pc && src2 != pc && srcA != pc);
1690 src2.code()*B8 | B7 | B4 | src1.code());
1694 void Assembler::mls(Register dst, Register src1, Register src2, Register srcA,
1696 DCHECK(dst != pc && src1 != pc && src2 != pc && srcA != pc);
1699 src2.code()*B8 | B7 | B4 | src1.code());
1703 void Assembler::sdiv(Register dst, Register src1, Register src2,
1705 DCHECK(dst != pc && src1 != pc && src2 != pc);
1708 src2.code() * B8 | B4 | src1.code());
1712 void Assembler::udiv(Register dst, Register src1, Register src2,
1714 DCHECK(dst != pc && src1 != pc && src2 != pc);
1717 src2.code() * B8 | B4 | src1.code());
1721 void Assembler::mul(Register dst, Register src1, Register src2, SBit s,
1723 DCHECK(dst != pc && src1 != pc && src2 != pc);
1725 emit(cond | s | dst.code() * B16 | src2.code() * B8 | B7 | B4 | src1.code());
1729 void Assembler::smmla(Register dst, Register src1, Register src2, Register srcA,
1731 DCHECK(dst != pc && src1 != pc && src2 != pc && srcA != pc);
1733 srcA.code() * B12 | src2.code() * B8 | B4 | src1.code());
1737 void Assembler::smmul(Register dst, Register src1, Register src2,
1739 DCHECK(dst != pc && src1 != pc && src2 != pc);
1741 src2.code() * B8 | B4 | src1.code());
1748 Register src2,
1751 DCHECK(dstL != pc && dstH != pc && src1 != pc && src2 != pc);
1754 src2.code()*B8 | B7 | B4 | src1.code());
1761 Register src2,
1764 DCHECK(dstL != pc && dstH != pc && src1 != pc && src2 != pc);
1767 src2.code()*B8 | B7 | B4 | src1.code());
1774 Register src2,
1777 DCHECK(dstL != pc && dstH != pc && src1 != pc && src2 != pc);
1780 src2.code()*B8 | B7 | B4 | src1.code());
1787 Register src2,
1790 DCHECK(dstL != pc && dstH != pc && src1 != pc && src2 != pc);
1793 src2.code()*B8 | B7 | B4 | src1.code());
1901 const Operand& src2,
1908 DCHECK(src2.IsImmediateShiftedRegister());
1909 DCHECK(src2.rm() != pc);
1910 DCHECK((src2.shift_imm_ >= 0) && (src2.shift_imm_ <= 31));
1911 DCHECK(src2.shift_op() == LSL);
1913 src2.shift_imm_*B7 | B4 | src2.rm().code());
1919 const Operand& src2,
1926 DCHECK(src2.IsImmediateShiftedRegister());
1927 DCHECK(src2.rm() != pc);
1928 DCHECK((src2.shift_imm_ >= 1) && (src2.shift_imm_ <= 32));
1929 DCHECK(src2.shift_op() == ASR);
1930 int asr = (src2.shift_imm_ == 32) ? 0 : src2.shift_imm_;
1932 asr*B7 | B6 | B4 | src2.rm().code());
1948 void Assembler::sxtab(Register dst, Register src1, Register src2, int rotate,
1955 DCHECK(src2 != pc);
1958 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src2.code());
1974 void Assembler::sxtah(Register dst, Register src1, Register src2, int rotate,
1981 DCHECK(src2 != pc);
1984 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src2.code());
2000 void Assembler::uxtab(Register dst, Register src1, Register src2, int rotate,
2007 DCHECK(src2 != pc);
2010 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src2.code());
2038 void Assembler::uxtah(Register dst, Register src1, Register src2, int rotate,
2045 DCHECK(src2 != pc);
2048 ((rotate >> 1) & 0xC) * B8 | 7 * B4 | src2.code());
2155 void Assembler::strd(Register src1, Register src2,
2160 DCHECK_EQ(src1.code() + 1, src2.code());
2183 void Assembler::strex(Register src1, Register src2, Register dst,
2190 DCHECK(src2 != pc);
2192 DCHECK(src1 != src2);
2194 src2.code());
2206 void Assembler::strexb(Register src1, Register src2, Register dst,
2213 DCHECK(src2 != pc);
2215 DCHECK(src1 != src2);
2217 0xF9 * B4 | src2.code());
2229 void Assembler::strexh(Register src1, Register src2, Register dst,
2236 DCHECK(src2 != pc);
2238 DCHECK(src1 != src2);
2240 0xF9 * B4 | src2.code());
2255 void Assembler::strexd(Register res, Register src1, Register src2, Register dst,
2262 DCHECK_EQ(src1.code() + 1, src2.code());
2925 const Register src2,
2932 DCHECK(src1 != pc && src2 != pc);
2935 emit(cond | 0xC*B24 | B22 | src2.code()*B16 |
3255 const DwVfpRegister src2,
3264 DCHECK(VfpRegisterIsAvailable(src2));
3270 src2.split_code(&vm, &m);
3277 const SwVfpRegister src2, const Condition cond) {
3288 src2.split_code(&vm, &m);
3296 const DwVfpRegister src2,
3305 DCHECK(VfpRegisterIsAvailable(src2));
3311 src2.split_code(&vm, &m);
3318 const SwVfpRegister src2, const Condition cond) {
3329 src2.split_code(&vm, &m);
3337 const DwVfpRegister src2,
3346 DCHECK(VfpRegisterIsAvailable(src2));
3352 src2.split_code(&vm, &m);
3359 const SwVfpRegister src2, const Condition cond) {
3370 src2.split_code(&vm, &m);
3378 const DwVfpRegister src2,
3385 DCHECK(VfpRegisterIsAvailable(src2));
3391 src2.split_code(&vm, &m);
3398 const SwVfpRegister src2, const Condition cond) {
3407 src2.split_code(&vm, &m);
3415 const DwVfpRegister src2,
3422 DCHECK(VfpRegisterIsAvailable(src2));
3428 src2.split_code(&vm, &m);
3435 const SwVfpRegister src2, const Condition cond) {
3444 src2.split_code(&vm, &m);
3452 const DwVfpRegister src2,
3461 DCHECK(VfpRegisterIsAvailable(src2));
3467 src2.split_code(&vm, &m);
3474 const SwVfpRegister src2, const Condition cond) {
3485 src2.split_code(&vm, &m);
3492 const DwVfpRegister src2,
3499 DCHECK(VfpRegisterIsAvailable(src2));
3503 src2.split_code(&vm, &m);
3509 void Assembler::vcmp(const SwVfpRegister src1, const SwVfpRegister src2,
3518 src2.split_code(&vm, &m);
3525 const double src2,
3532 DCHECK_EQ(src2, 0.0);
3539 void Assembler::vcmp(const SwVfpRegister src1, const float src2,
3545 DCHECK_EQ(src2, 0.0);
3553 const DwVfpRegister src2) {
3562 src2.split_code(&vm, &m);
3569 const SwVfpRegister src2) {
3578 src2.split_code(&vm, &m);
3585 const DwVfpRegister src2) {
3594 src2.split_code(&vm, &m);
3601 const SwVfpRegister src2) {
3610 src2.split_code(&vm, &m);
3617 const DwVfpRegister src1, const DwVfpRegister src2) {
3627 src2.split_code(&vm, &m);
3649 const SwVfpRegister src1, const SwVfpRegister src2) {
3659 src2.split_code(&vm, &m);
4239 QwNeonRegister src2) {
4244 src2.code()));
4248 QwNeonRegister src2) {
4253 src2.code()));
4257 DwVfpRegister src2) {
4262 src2.code()));
4266 QwNeonRegister src2) {
4271 src2.code()));
4275 QwNeonRegister src2) {
4280 src2.code()));
4297 QwNeonRegister src1, QwNeonRegister src2) {
4339 src2.split_code(&vm, &m);
4360 QwNeonRegister src2) {
4405 src2.split_code(&vm, &m);
4413 QwNeonRegister src1, QwNeonRegister src2) {
4416 return EncodeNeonBinOp(op, static_cast<NeonDataType>(size), dst, src1, src2);
4420 QwNeonRegister src2) {
4424 emit(EncodeNeonBinOp(VADDF, dst, src1, src2));
4428 QwNeonRegister src2) {
4432 emit(EncodeNeonBinOp(VADD, size, dst, src1, src2));
4436 QwNeonRegister src2) {
4440 emit(EncodeNeonBinOp(VQADD, dt, dst, src1, src2));
4444 QwNeonRegister src2) {
4448 emit(EncodeNeonBinOp(VSUBF, dst, src1, src2));
4452 QwNeonRegister src2) {
4456 emit(EncodeNeonBinOp(VSUB, size, dst, src1, src2));
4460 QwNeonRegister src2) {
4464 emit(EncodeNeonBinOp(VQSUB, dt, dst, src1, src2));
4468 QwNeonRegister src2) {
4472 emit(EncodeNeonBinOp(VMULF, dst, src1, src2));
4476 QwNeonRegister src2) {
4480 emit(EncodeNeonBinOp(VMUL, size, dst, src1, src2));
4484 QwNeonRegister src2) {
4488 emit(EncodeNeonBinOp(VMINF, dst, src1, src2));
4492 QwNeonRegister src2) {
4496 emit(EncodeNeonBinOp(VMIN, dt, dst, src1, src2));
4500 QwNeonRegister src2) {
4504 emit(EncodeNeonBinOp(VMAXF, dst, src1, src2));
4508 QwNeonRegister src2) {
4512 emit(EncodeNeonBinOp(VMAX, dt, dst, src1, src2));
4628 QwNeonRegister src2) {
4632 emit(EncodeNeonBinOp(VRECPS, dst, src1, src2));
4636 QwNeonRegister src2) {
4640 emit(EncodeNeonBinOp(VRSQRTS, dst, src1, src2));
4647 DwVfpRegister src2) {
4668 src2.split_code(&vm, &m);
4676 DwVfpRegister src2) {
4685 src2.split_code(&vm, &m);
4692 DwVfpRegister src2) {
4696 emit(EncodeNeonPairwiseOp(VPADD, NeonSizeToDataType(size), dst, src1, src2));
4700 DwVfpRegister src2) {
4704 emit(EncodeNeonPairwiseOp(VPMIN, dt, dst, src1, src2));
4708 DwVfpRegister src2) {
4712 emit(EncodeNeonPairwiseOp(VPMAX, dt, dst, src1, src2));
4716 QwNeonRegister src2) {
4720 emit(EncodeNeonBinOp(VTST, size, dst, src1, src2));
4724 QwNeonRegister src2) {
4728 emit(EncodeNeonBinOp(VCEQF, dst, src1, src2));
4732 QwNeonRegister src2) {
4736 emit(EncodeNeonBinOp(VCEQ, size, dst, src1, src2));
4740 QwNeonRegister src2) {
4744 emit(EncodeNeonBinOp(VCGEF, dst, src1, src2));
4748 QwNeonRegister src2) {
4752 emit(EncodeNeonBinOp(VCGE, dt, dst, src1, src2));
4756 QwNeonRegister src2) {
4760 emit(EncodeNeonBinOp(VCGTF, dst, src1, src2));
4764 QwNeonRegister src2) {
4768 emit(EncodeNeonBinOp(VCGT, dt, dst, src1, src2));
4772 QwNeonRegister src2, int bytes) {
4781 src2.split_code(&vm, &m);
4825 void Assembler::vzip(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) {
4827 vtrn(size, src1, src2);
4832 emit(EncodeNeonSizedOp(VZIP, NEON_D, size, src1.code(), src2.code()));
4836 void Assembler::vzip(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) {
4840 emit(EncodeNeonSizedOp(VZIP, NEON_Q, size, src1.code(), src2.code()));
4843 void Assembler::vuzp(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) {
4845 vtrn(size, src1, src2);
4850 emit(EncodeNeonSizedOp(VUZP, NEON_D, size, src1.code(), src2.code()));
4854 void Assembler::vuzp(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) {
4858 emit(EncodeNeonSizedOp(VUZP, NEON_Q, size, src1.code(), src2.code()));
4882 void Assembler::vtrn(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) {
4886 emit(EncodeNeonSizedOp(VTRN, NEON_D, size, src1.code(), src2.code()));
4889 void Assembler::vtrn(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) {
4893 emit(EncodeNeonSizedOp(VTRN, NEON_Q, size, src1.code(), src2.code()));
