Lines Matching refs:src2
587 const LogicVRegister& src2, Condition cond) {
591 int64_t sb = src2.Int(vform, i);
593 uint64_t ub = src2.Uint(vform, i);
635 const LogicVRegister& src2) {
639 uint64_t ub = src2.Uint(vform, i);
647 const LogicVRegister& src2) {
653 uint64_t ub = src2.UintLeftJustified(vform, i);
676 const LogicVRegister& src2) {
678 uzp1(vform, temp1, src1, src2);
679 uzp2(vform, temp2, src1, src2);
686 const LogicVRegister& src2) {
688 mul(vform, temp, src1, src2);
695 const LogicVRegister& src2) {
697 mul(vform, temp, src1, src2);
704 const LogicVRegister& src2) {
707 dst.SetUint(vform, i, src1.Uint(vform, i) * src2.Uint(vform, i));
714 const LogicVRegister& src2, int index) {
717 return mul(vform, dst, src1, dup_element(indexform, temp, src2, index));
722 const LogicVRegister& src2, int index) {
725 return mla(vform, dst, src1, dup_element(indexform, temp, src2, index));
730 const LogicVRegister& src2, int index) {
733 return mls(vform, dst, src1, dup_element(indexform, temp, src2, index));
738 const LogicVRegister& src2, int index) {
742 return smull(vform, dst, src1, dup_element(indexform, temp, src2, index));
747 const LogicVRegister& src2, int index) {
751 return smull2(vform, dst, src1, dup_element(indexform, temp, src2, index));
756 const LogicVRegister& src2, int index) {
760 return umull(vform, dst, src1, dup_element(indexform, temp, src2, index));
765 const LogicVRegister& src2, int index) {
769 return umull2(vform, dst, src1, dup_element(indexform, temp, src2, index));
774 const LogicVRegister& src2, int index) {
778 return smlal(vform, dst, src1, dup_element(indexform, temp, src2, index));
783 const LogicVRegister& src2, int index) {
787 return smlal2(vform, dst, src1, dup_element(indexform, temp, src2, index));
792 const LogicVRegister& src2, int index) {
796 return umlal(vform, dst, src1, dup_element(indexform, temp, src2, index));
801 const LogicVRegister& src2, int index) {
805 return umlal2(vform, dst, src1, dup_element(indexform, temp, src2, index));
810 const LogicVRegister& src2, int index) {
814 return smlsl(vform, dst, src1, dup_element(indexform, temp, src2, index));
819 const LogicVRegister& src2, int index) {
823 return smlsl2(vform, dst, src1, dup_element(indexform, temp, src2, index));
828 const LogicVRegister& src2, int index) {
832 return umlsl(vform, dst, src1, dup_element(indexform, temp, src2, index));
837 const LogicVRegister& src2, int index) {
841 return umlsl2(vform, dst, src1, dup_element(indexform, temp, src2, index));
846 const LogicVRegister& src2, int index) {
850 return sqdmull(vform, dst, src1, dup_element(indexform, temp, src2, index));
855 const LogicVRegister& src2, int index) {
859 return sqdmull2(vform, dst, src1, dup_element(indexform, temp, src2, index));
864 const LogicVRegister& src2, int index) {
868 return sqdmlal(vform, dst, src1, dup_element(indexform, temp, src2, index));
873 const LogicVRegister& src2, int index) {
877 return sqdmlal2(vform, dst, src1, dup_element(indexform, temp, src2, index));
882 const LogicVRegister& src2, int index) {
886 return sqdmlsl(vform, dst, src1, dup_element(indexform, temp, src2, index));
891 const LogicVRegister& src2, int index) {
895 return sqdmlsl2(vform, dst, src1, dup_element(indexform, temp, src2, index));
900 const LogicVRegister& src2, int index) {
903 return sqdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index));
908 const LogicVRegister& src2, int index) {
911 return sqrdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index));
927 const LogicVRegister& src2) {
931 PolynomialMult(src1.Uint(vform, i), src2.Uint(vform, i)));
938 const LogicVRegister& src2) {
944 PolynomialMult(src1.Uint(vform_src, i), src2.Uint(vform_src, i)));
951 const LogicVRegister& src2) {
958 src2.Uint(vform_src, lane_count + i)));
965 const LogicVRegister& src2) {
971 uint64_t ub = src2.UintLeftJustified(vform, i);
994 const LogicVRegister& src2) {
997 dst.SetUint(vform, i, src1.Uint(vform, i) & src2.Uint(vform, i));
1004 const LogicVRegister& src2) {
1007 dst.SetUint(vform, i, src1.Uint(vform, i) | src2.Uint(vform, i));
1014 const LogicVRegister& src2) {
1017 dst.SetUint(vform, i, src1.Uint(vform, i) | ~src2.Uint(vform, i));
1024 const LogicVRegister& src2) {
1027 dst.SetUint(vform, i, src1.Uint(vform, i) ^ src2.Uint(vform, i));
1034 const LogicVRegister& src2) {
1037 dst.SetUint(vform, i, src1.Uint(vform, i) & ~src2.Uint(vform, i));
1055 const LogicVRegister& src2) {
1059 uint64_t operand2 = ~src2.Uint(vform, i);
1069 const LogicVRegister& src2) {
1073 uint64_t operand2 = src2.Uint(vform, i);
1083 const LogicVRegister& src2) {
1086 uint64_t operand1 = src2.Uint(vform, i);
1097 const LogicVRegister& src2, bool max) {
1101 int64_t src2_val = src2.Int(vform, i);
1115 const LogicVRegister& src2) {
1116 return SMinMax(vform, dst, src1, src2, true);
1121 const LogicVRegister& src2) {
1122 return SMinMax(vform, dst, src1, src2, false);
1127 const LogicVRegister& src2, bool max) {
1144 src = &src2;
1152 const LogicVRegister& src2) {
1153 return SMinMaxP(vform, dst, src1, src2, true);
1158 const LogicVRegister& src2) {
1159 return SMinMaxP(vform, dst, src1, src2, false);
1247 const LogicVRegister& src2, bool max) {
1251 uint64_t src2_val = src2.Uint(vform, i);
1265 const LogicVRegister& src2) {
1266 return UMinMax(vform, dst, src1, src2, true);
1271 const LogicVRegister& src2) {
1272 return UMinMax(vform, dst, src1, src2, false);
1277 const LogicVRegister& src2, bool max) {
1294 src = &src2;
1302 const LogicVRegister& src2) {
1303 return UMinMaxP(vform, dst, src1, src2, true);
1308 const LogicVRegister& src2) {
1309 return UMinMaxP(vform, dst, src1, src2, false);
1547 const LogicVRegister& src2) {
1550 int8_t shift_val = src2.Int(vform, i);
1606 const LogicVRegister& src2) {
1609 int8_t shift_val = src2.Int(vform, i);
1832 const LogicVRegister& src2, bool issigned) {
1836 int64_t sr = src1.Int(vform, i) - src2.Int(vform, i);
1840 int64_t sr = src1.Uint(vform, i) - src2.Uint(vform, i);
1850 const LogicVRegister& src2) {
1853 AbsDiff(vform, temp, src1, src2, true);
1860 const LogicVRegister& src2) {
1863 AbsDiff(vform, temp, src1, src2, false);
1979 const LogicVRegister& src2, int index) {
1986 result[laneCount - index + i] = src2.Uint(vform, i);
2324 const LogicVRegister& src2) {
2327 uxtl(vform, temp2, src2);
2334 const LogicVRegister& src2) {
2337 uxtl2(vform, temp2, src2);
2344 const LogicVRegister& src2) {
2346 uxtl(vform, temp, src2);
2353 const LogicVRegister& src2) {
2355 uxtl2(vform, temp, src2);
2362 const LogicVRegister& src2) {
2365 sxtl(vform, temp2, src2);
2372 const LogicVRegister& src2) {
2375 sxtl2(vform, temp2, src2);
2382 const LogicVRegister& src2) {
2384 sxtl(vform, temp, src2);
2391 const LogicVRegister& src2) {
2393 sxtl2(vform, temp, src2);
2400 const LogicVRegister& src2) {
2403 uxtl(vform, temp2, src2);
2410 const LogicVRegister& src2) {
2413 uxtl2(vform, temp2, src2);
2420 const LogicVRegister& src2) {
2422 uxtl(vform, temp, src2);
2429 const LogicVRegister& src2) {
2431 uxtl2(vform, temp, src2);
2438 const LogicVRegister& src2) {
2441 sxtl(vform, temp2, src2);
2448 const LogicVRegister& src2) {
2451 sxtl2(vform, temp2, src2);
2458 const LogicVRegister& src2) {
2460 sxtl(vform, temp, src2);
2467 const LogicVRegister& src2) {
2469 sxtl2(vform, temp, src2);
2476 const LogicVRegister& src2) {
2479 uxtl(vform, temp2, src2);
2486 const LogicVRegister& src2) {
2489 uxtl2(vform, temp2, src2);
2496 const LogicVRegister& src2) {
2499 sxtl(vform, temp2, src2);
2506 const LogicVRegister& src2) {
2509 sxtl2(vform, temp2, src2);
2516 const LogicVRegister& src2) {
2519 uxtl(vform, temp2, src2);
2526 const LogicVRegister& src2) {
2529 uxtl2(vform, temp2, src2);
2536 const LogicVRegister& src2) {
2539 sxtl(vform, temp2, src2);
2546 const LogicVRegister& src2) {
2549 sxtl2(vform, temp2, src2);
2556 const LogicVRegister& src2) {
2559 uxtl(vform, temp2, src2);
2566 const LogicVRegister& src2) {
2569 uxtl2(vform, temp2, src2);
2576 const LogicVRegister& src2) {
2579 sxtl(vform, temp2, src2);
2586 const LogicVRegister& src2) {
2589 sxtl2(vform, temp2, src2);
2596 const LogicVRegister& src2) {
2599 uxtl(vform, temp2, src2);
2606 const LogicVRegister& src2) {
2609 uxtl2(vform, temp2, src2);
2616 const LogicVRegister& src2) {
2619 sxtl(vform, temp2, src2);
2626 const LogicVRegister& src2) {
2629 sxtl2(vform, temp2, src2);
2636 const LogicVRegister& src2) {
2639 uxtl(vform, temp2, src2);
2646 const LogicVRegister& src2) {
2649 uxtl2(vform, temp2, src2);
2656 const LogicVRegister& src2) {
2659 sxtl(vform, temp2, src2);
2666 const LogicVRegister& src2) {
2669 sxtl2(vform, temp2, src2);
2676 const LogicVRegister& src2) {
2678 LogicVRegister product = sqdmull(vform, temp, src1, src2);
2684 const LogicVRegister& src2) {
2686 LogicVRegister product = sqdmull2(vform, temp, src1, src2);
2692 const LogicVRegister& src2) {
2694 LogicVRegister product = sqdmull(vform, temp, src1, src2);
2700 const LogicVRegister& src2) {
2702 LogicVRegister product = sqdmull2(vform, temp, src1, src2);
2708 const LogicVRegister& src2) {
2710 LogicVRegister product = smull(vform, temp, src1, src2);
2716 const LogicVRegister& src2) {
2718 LogicVRegister product = smull2(vform, temp, src1, src2);
2724 const LogicVRegister& src2, bool round) {
2726 // To avoid this, we use (src1 * src2 + 1 << (esize - 2)) >> (esize - 1)
2727 // which is same as (2 * src1 * src2 + 1 << (esize - 1)) >> esize.
2735 product = src1.Int(vform, i) * src2.Int(vform, i);
2751 const LogicVRegister& src2) {
2752 return sqrdmulh(vform, dst, src1, src2, false);
2757 const LogicVRegister& src2) {
2759 add(VectorFormatDoubleWidth(vform), temp, src1, src2);
2766 const LogicVRegister& src2) {
2768 add(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
2775 const LogicVRegister& src2) {
2777 add(VectorFormatDoubleWidth(vform), temp, src1, src2);
2784 const LogicVRegister& src2) {
2786 add(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
2793 const LogicVRegister& src2) {
2795 sub(VectorFormatDoubleWidth(vform), temp, src1, src2);
2802 const LogicVRegister& src2) {
2804 sub(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
2811 const LogicVRegister& src2) {
2813 sub(VectorFormatDoubleWidth(vform), temp, src1, src2);
2820 const LogicVRegister& src2) {
2822 sub(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
2829 const LogicVRegister& src2) {
2835 result[(2 * i) + 1] = src2.Uint(vform, 2 * i);
2844 const LogicVRegister& src2) {
2850 result[(2 * i) + 1] = src2.Uint(vform, (2 * i) + 1);
2859 const LogicVRegister& src2) {
2865 result[(2 * i) + 1] = src2.Uint(vform, i);
2874 const LogicVRegister& src2) {
2880 result[(2 * i) + 1] = src2.Uint(vform, pairs + i);
2889 const LogicVRegister& src2) {
2894 result[laneCount + i] = src2.Uint(vform, i);
2906 const LogicVRegister& src2) {
2911 result[laneCount + i] = src2.Uint(vform, i);
3263 const LogicVRegister& src2) { \
3267 T op2 = src2.Float<T>(i); \
3284 const LogicVRegister& src2) { \
3286 FN<float>(vform, dst, src1, src2); \
3289 FN<double>(vform, dst, src1, src2); \
3298 const LogicVRegister& src2) {
3300 LogicVRegister product = fmul(vform, temp, src1, src2);
3307 const LogicVRegister& src2) {
3311 T op2 = src2.Float<T>(i);
3320 const LogicVRegister& src2) {
3322 frecps<float>(vform, dst, src1, src2);
3325 frecps<double>(vform, dst, src1, src2);
3333 const LogicVRegister& src2) {
3337 T op2 = src2.Float<T>(i);
3346 const LogicVRegister& src2) {
3348 frsqrts<float>(vform, dst, src1, src2);
3351 frsqrts<double>(vform, dst, src1, src2);
3359 const LogicVRegister& src2, Condition cond) {
3364 T op2 = src2.Float<T>(i);
3394 const LogicVRegister& src2, Condition cond) {
3396 fcmp<float>(vform, dst, src1, src2, cond);
3399 fcmp<double>(vform, dst, src1, src2, cond);
3422 const LogicVRegister& src2, Condition cond) {
3426 LogicVRegister abs_src2 = fabs_<float>(vform, temp2, src2);
3431 LogicVRegister abs_src2 = fabs_<double>(vform, temp2, src2);
3440 const LogicVRegister& src2) {
3444 T op2 = src2.Float<T>(i);
3454 const LogicVRegister& src2) {
3456 fmla<float>(vform, dst, src1, src2);
3459 fmla<double>(vform, dst, src1, src2);
3467 const LogicVRegister& src2) {
3471 T op2 = src2.Float<T>(i);
3481 const LogicVRegister& src2) {
3483 fmls<float>(vform, dst, src1, src2);
3486 fmls<double>(vform, dst, src1, src2);
3541 const LogicVRegister& src2) {
3543 fsub(vform, temp, src1, src2);
3569 const LogicVRegister& src2) { \
3571 uzp1(vform, temp1, src1, src2); \
3572 uzp2(vform, temp2, src1, src2); \
3627 const LogicVRegister& src2, int index) {
3631 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
3635 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index);
3643 const LogicVRegister& src2, int index) {
3647 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
3651 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index);
3659 const LogicVRegister& src2, int index) {
3663 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
3667 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index);
3675 const LogicVRegister& src2, int index) {
3679 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
3684 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index);
