Lines Matching refs:src2
481 const LogicVRegister& src2,
486 int64_t sb = src2.Int(vform, i);
488 uint64_t ub = src2.Uint(vform, i);
536 const LogicVRegister& src2) {
540 uint64_t ub = src2.Uint(vform, i);
550 const LogicVRegister& src2) {
556 uint64_t ub = src2.UintLeftJustified(vform, i);
581 const LogicVRegister& src2) {
583 uzp1(vform, temp1, src1, src2);
584 uzp2(vform, temp2, src1, src2);
593 const LogicVRegister& src2) {
595 mul(vform, temp, src1, src2);
604 const LogicVRegister& src2) {
606 mul(vform, temp, src1, src2);
615 const LogicVRegister& src2) {
618 dst.SetUint(vform, i, src1.Uint(vform, i) * src2.Uint(vform, i));
627 const LogicVRegister& src2,
631 return mul(vform, dst, src1, dup_element(indexform, temp, src2, index));
638 const LogicVRegister& src2,
642 return mla(vform, dst, src1, dup_element(indexform, temp, src2, index));
649 const LogicVRegister& src2,
653 return mls(vform, dst, src1, dup_element(indexform, temp, src2, index));
660 const LogicVRegister& src2,
665 return smull(vform, dst, src1, dup_element(indexform, temp, src2, index));
672 const LogicVRegister& src2,
677 return smull2(vform, dst, src1, dup_element(indexform, temp, src2, index));
684 const LogicVRegister& src2,
689 return umull(vform, dst, src1, dup_element(indexform, temp, src2, index));
696 const LogicVRegister& src2,
701 return umull2(vform, dst, src1, dup_element(indexform, temp, src2, index));
708 const LogicVRegister& src2,
713 return smlal(vform, dst, src1, dup_element(indexform, temp, src2, index));
720 const LogicVRegister& src2,
725 return smlal2(vform, dst, src1, dup_element(indexform, temp, src2, index));
732 const LogicVRegister& src2,
737 return umlal(vform, dst, src1, dup_element(indexform, temp, src2, index));
744 const LogicVRegister& src2,
749 return umlal2(vform, dst, src1, dup_element(indexform, temp, src2, index));
756 const LogicVRegister& src2,
761 return smlsl(vform, dst, src1, dup_element(indexform, temp, src2, index));
768 const LogicVRegister& src2,
773 return smlsl2(vform, dst, src1, dup_element(indexform, temp, src2, index));
780 const LogicVRegister& src2,
785 return umlsl(vform, dst, src1, dup_element(indexform, temp, src2, index));
792 const LogicVRegister& src2,
797 return umlsl2(vform, dst, src1, dup_element(indexform, temp, src2, index));
804 const LogicVRegister& src2,
809 return sqdmull(vform, dst, src1, dup_element(indexform, temp, src2, index));
816 const LogicVRegister& src2,
821 return sqdmull2(vform, dst, src1, dup_element(indexform, temp, src2, index));
828 const LogicVRegister& src2,
833 return sqdmlal(vform, dst, src1, dup_element(indexform, temp, src2, index));
840 const LogicVRegister& src2,
845 return sqdmlal2(vform, dst, src1, dup_element(indexform, temp, src2, index));
852 const LogicVRegister& src2,
857 return sqdmlsl(vform, dst, src1, dup_element(indexform, temp, src2, index));
864 const LogicVRegister& src2,
869 return sqdmlsl2(vform, dst, src1, dup_element(indexform, temp, src2, index));
876 const LogicVRegister& src2,
880 return sqdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index));
887 const LogicVRegister& src2,
891 return sqrdmulh(vform, dst, src1, dup_element(indexform, temp, src2, index));
898 const LogicVRegister& src2,
902 return sdot(vform, dst, src1, dup_element(indexform, temp, src2, index));
909 const LogicVRegister& src2,
913 return sqrdmlah(vform, dst, src1, dup_element(indexform, temp, src2, index));
920 const LogicVRegister& src2,
924 return udot(vform, dst, src1, dup_element(indexform, temp, src2, index));
931 const LogicVRegister& src2,
935 return sqrdmlsh(vform, dst, src1, dup_element(indexform, temp, src2, index));
954 const LogicVRegister& src2) {
959 PolynomialMult(src1.Uint(vform, i), src2.Uint(vform, i)));
968 const LogicVRegister& src2) {
975 src2.Uint(vform_src, i)));
984 src2) {
992 src2.Uint(vform_src, lane_count + i)));
1001 const LogicVRegister& src2) {
1007 uint64_t ub = src2.UintLeftJustified(vform, i);
1032 const LogicVRegister& src2) {
1035 dst.SetUint(vform, i, src1.Uint(vform, i) & src2.Uint(vform, i));
1044 const LogicVRegister& src2) {
1047 dst.SetUint(vform, i, src1.Uint(vform, i) | src2.Uint(vform, i));
1056 const LogicVRegister& src2) {
1059 dst.SetUint(vform, i, src1.Uint(vform, i) | ~src2.Uint(vform, i));
1068 const LogicVRegister& src2) {
1071 dst.SetUint(vform, i, src1.Uint(vform, i) ^ src2.Uint(vform, i));
1080 const LogicVRegister& src2) {
1083 dst.SetUint(vform, i, src1.Uint(vform, i) & ~src2.Uint(vform, i));
1109 const LogicVRegister& src2) {
1113 uint64_t operand2 = ~src2.Uint(vform, i);
1125 const LogicVRegister& src2) {
1129 uint64_t operand2 = src2.Uint(vform, i);
1141 const LogicVRegister& src2) {
1144 uint64_t operand1 = src2.Uint(vform, i);
1157 const LogicVRegister& src2,
1162 int64_t src2_val = src2.Int(vform, i);
1178 const LogicVRegister& src2) {
1179 return sminmax(vform, dst, src1, src2, true);
1186 const LogicVRegister& src2) {
1187 return sminmax(vform, dst, src1, src2, false);
1194 const LogicVRegister& src2,
1212 src = &src2;
1222 const LogicVRegister& src2) {
1223 return sminmaxp(vform, dst, src1, src2, true);
1230 const LogicVRegister& src2) {
1231 return sminmaxp(vform, dst, src1, src2, false);
1337 const LogicVRegister& src2,
1342 uint64_t src2_val = src2.Uint(vform, i);
1358 const LogicVRegister& src2) {
1359 return uminmax(vform, dst, src1, src2, true);
1366 const LogicVRegister& src2) {
1367 return uminmax(vform, dst, src1, src2, false);
1374 const LogicVRegister& src2,
1392 src = &src2;
1402 const LogicVRegister& src2) {
1403 return uminmaxp(vform, dst, src1, src2, true);
1410 const LogicVRegister& src2) {
1411 return uminmaxp(vform, dst, src1, src2, false);
1725 const LogicVRegister& src2) {
1728 int8_t shift_val = src2.Int(vform, i);
1785 const LogicVRegister& src2) {
1788 int8_t shift_val = src2.Int(vform, i);
2032 const LogicVRegister& src2,
2037 int64_t sr = src1.Int(vform, i) - src2.Int(vform, i);
2041 int64_t sr = src1.Uint(vform, i) - src2.Uint(vform, i);
2053 const LogicVRegister& src2) {
2056 absdiff(vform, temp, src1, src2, true);
2065 const LogicVRegister& src2) {
2068 absdiff(vform, temp, src1, src2, false);
2216 const LogicVRegister& src2,
2224 result[laneCount - index + i] = src2.Uint(vform, i);
2237 const LogicVRegister& src2, // m
2251 element1 = FPNeg(src2.Float<T>(e * 2 + 1));
2252 element3 = src2.Float<T>(e * 2);
2255 element1 = src2.Float<T>(e * 2 + 1);
2256 element3 = FPNeg(src2.Float<T>(e * 2));
2273 const LogicVRegister& src2, // m
2278 fcadd<float>(vform, dst, src1, src2, rot);
2281 fcadd<double>(vform, dst, src1, src2, rot);
2291 const LogicVRegister& src2, // m
2306 element1 = src2.Float<T>(index * 2);
2308 element3 = src2.Float<T>(index * 2 + 1);
2312 element1 = FPNeg(src2.Float<T>(index * 2 + 1));
2314 element3 = src2.Float<T>(index * 2);
2318 element1 = FPNeg(src2.Float<T>(index * 2));
2320 element3 = FPNeg(src2.Float<T>(index * 2 + 1));
2324 element1 = src2.Float<T>(index * 2 + 1);
2326 element3 = FPNeg(src2.Float<T>(index * 2));
2346 const LogicVRegister& src2, // m
2360 element1 = src2.Float<T>(e * 2);
2362 element3 = src2.Float<T>(e * 2 + 1);
2366 element1 = FPNeg(src2.Float<T>(e * 2 + 1));
2368 element3 = src2.Float<T>(e * 2);
2372 element1 = FPNeg(src2.Float<T>(e * 2));
2374 element3 = FPNeg(src2.Float<T>(e * 2 + 1));
2378 element1 = src2.Float<T>(e * 2 + 1);
2380 element3 = FPNeg(src2.Float<T>(e * 2));
2399 const LogicVRegister& src2, // m
2404 fcmla<float>(vform, dst, src1, src2, rot);
2406 fcmla<double>(vform, dst, src1, src2, rot);
2415 const LogicVRegister& src2, // m
2421 fcmla<float>(vform, dst, src1, src2, index, rot);
2423 fcmla<double>(vform, dst, src1, src2, index, rot);
2853 const LogicVRegister& src2) {
2856 uxtl(vform, temp2, src2);
2865 const LogicVRegister& src2) {
2868 uxtl2(vform, temp2, src2);
2877 const LogicVRegister& src2) {
2879 uxtl(vform, temp, src2);
2888 const LogicVRegister& src2) {
2890 uxtl2(vform, temp, src2);
2899 const LogicVRegister& src2) {
2902 sxtl(vform, temp2, src2);
2911 const LogicVRegister& src2) {
2914 sxtl2(vform, temp2, src2);
2923 const LogicVRegister& src2) {
2925 sxtl(vform, temp, src2);
2934 const LogicVRegister& src2) {
2936 sxtl2(vform, temp, src2);
2945 const LogicVRegister& src2) {
2948 uxtl(vform, temp2, src2);
2957 const LogicVRegister& src2) {
2960 uxtl2(vform, temp2, src2);
2969 const LogicVRegister& src2) {
2971 uxtl(vform, temp, src2);
2980 const LogicVRegister& src2) {
2982 uxtl2(vform, temp, src2);
2991 const LogicVRegister& src2) {
2994 sxtl(vform, temp2, src2);
3003 const LogicVRegister& src2) {
3006 sxtl2(vform, temp2, src2);
3015 const LogicVRegister& src2) {
3017 sxtl(vform, temp, src2);
3026 const LogicVRegister& src2) {
3028 sxtl2(vform, temp, src2);
3037 const LogicVRegister& src2) {
3040 uxtl(vform, temp2, src2);
3049 const LogicVRegister& src2) {
3052 uxtl2(vform, temp2, src2);
3061 const LogicVRegister& src2) {
3064 sxtl(vform, temp2, src2);
3073 const LogicVRegister& src2) {
3076 sxtl2(vform, temp2, src2);
3085 const LogicVRegister& src2) {
3088 uxtl(vform, temp2, src2);
3097 const LogicVRegister& src2) {
3100 uxtl2(vform, temp2, src2);
3109 const LogicVRegister& src2) {
3112 sxtl(vform, temp2, src2);
3121 const LogicVRegister& src2) {
3124 sxtl2(vform, temp2, src2);
3133 const LogicVRegister& src2) {
3136 uxtl(vform, temp2, src2);
3145 const LogicVRegister& src2) {
3148 uxtl2(vform, temp2, src2);
3157 const LogicVRegister& src2) {
3160 sxtl(vform, temp2, src2);
3169 const LogicVRegister& src2) {
3172 sxtl2(vform, temp2, src2);
3181 const LogicVRegister& src2) {
3184 uxtl(vform, temp2, src2);
3193 const LogicVRegister& src2) {
3196 uxtl2(vform, temp2, src2);
3205 const LogicVRegister& src2) {
3208 sxtl(vform, temp2, src2);
3217 const LogicVRegister& src2) {
3220 sxtl2(vform, temp2, src2);
3229 const LogicVRegister& src2) {
3232 uxtl(vform, temp2, src2);
3241 const LogicVRegister& src2) {
3244 uxtl2(vform, temp2, src2);
3253 const LogicVRegister& src2) {
3256 sxtl(vform, temp2, src2);
3265 const LogicVRegister& src2) {
3268 sxtl2(vform, temp2, src2);
3277 const LogicVRegister& src2) {
3279 LogicVRegister product = sqdmull(vform, temp, src1, src2);
3287 const LogicVRegister& src2) {
3289 LogicVRegister product = sqdmull2(vform, temp, src1, src2);
3297 const LogicVRegister& src2) {
3299 LogicVRegister product = sqdmull(vform, temp, src1, src2);
3307 const LogicVRegister& src2) {
3309 LogicVRegister product = sqdmull2(vform, temp, src1, src2);
3317 const LogicVRegister& src2) {
3319 LogicVRegister product = smull(vform, temp, src1, src2);
3327 const LogicVRegister& src2) {
3329 LogicVRegister product = smull2(vform, temp, src1, src2);
3337 const LogicVRegister& src2,
3340 // To avoid this, we use (src1 * src2 + 1 << (esize - 2)) >> (esize - 1)
3341 // which is same as (2 * src1 * src2 + 1 << (esize - 1)) >> esize.
3349 product = src1.Int(vform, i) * src2.Int(vform, i);
3367 const LogicVRegister& src2,
3380 element2 = src2.Int(quarter_vform, index);
3383 element2 = src2.Uint(quarter_vform, index);
3398 const LogicVRegister& src2) {
3399 return dot(vform, dst, src1, src2, true);
3406 const LogicVRegister& src2) {
3407 return dot(vform, dst, src1, src2, false);
3414 const LogicVRegister& src2,
3419 // (dst << (esize - 1) + src1 * src2 + 1 << (esize - 2)) >> (esize - 1)
3421 // (dst << esize + 2 * src1 * src2 + 1 << (esize - 1)) >> esize.
3431 accum -= src1.Int(vform, i) * src2.Int(vform, i);
3433 accum += src1.Int(vform, i) * src2.Int(vform, i);
3452 const LogicVRegister& src2,
3454 return sqrdmlash(vform, dst, src1, src2, round, false);
3461 const LogicVRegister& src2,
3463 return sqrdmlash(vform, dst, src1, src2, round, true);
3470 const LogicVRegister& src2) {
3471 return sqrdmulh(vform, dst, src1, src2, false);
3478 const LogicVRegister& src2) {
3480 add(VectorFormatDoubleWidth(vform), temp, src1, src2);
3489 const LogicVRegister& src2) {
3491 add(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
3500 src2) {
3502 add(VectorFormatDoubleWidth(vform), temp, src1, src2);
3511 const LogicVRegister& src2) {
3513 add(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
3522 const LogicVRegister& src2) {
3524 sub(VectorFormatDoubleWidth(vform), temp, src1, src2);
3533 const LogicVRegister& src2) {
3535 sub(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
3544 const LogicVRegister& src2) {
3546 sub(VectorFormatDoubleWidth(vform), temp, src1, src2);
3555 const LogicVRegister& src2) {
3557 sub(VectorFormatDoubleWidth(VectorFormatHalfLanes(vform)), temp, src1, src2);
3566 const LogicVRegister& src2) {
3572 result[(2 * i) + 1] = src2.Uint(vform, 2 * i);
3586 const LogicVRegister& src2) {
3592 result[(2 * i) + 1] = src2.Uint(vform, (2 * i) + 1);
3606 const LogicVRegister& src2) {
3612 result[(2 * i) + 1] = src2.Uint(vform, i);
3626 const LogicVRegister& src2) {
3632 result[(2 * i) + 1] = src2.Uint(vform, pairs + i);
3646 const LogicVRegister& src2) {
3651 result[laneCount + i] = src2.Uint(vform, i);
3665 const LogicVRegister& src2) {
3670 result[laneCount + i] = src2.Uint(vform, i);
4150 const LogicVRegister& src2) { \
4154 T op2 = src2.Float<T>(i); \
4172 const LogicVRegister& src2) { \
4174 FN<SimFloat16>(vform, dst, src1, src2); \
4176 FN<float>(vform, dst, src1, src2); \
4179 FN<double>(vform, dst, src1, src2); \
4190 const LogicVRegister& src2) {
4192 LogicVRegister product = fmul(vform, temp, src1, src2);
4201 const LogicVRegister& src2) {
4205 T op2 = src2.Float<T>(i);
4216 const LogicVRegister& src2) {
4218 frecps<SimFloat16>(vform, dst, src1, src2);
4220 frecps<float>(vform, dst, src1, src2);
4223 frecps<double>(vform, dst, src1, src2);
4233 const LogicVRegister& src2) {
4237 T op2 = src2.Float<T>(i);
4248 const LogicVRegister& src2) {
4250 frsqrts<SimFloat16>(vform, dst, src1, src2);
4252 frsqrts<float>(vform, dst, src1, src2);
4255 frsqrts<double>(vform, dst, src1, src2);
4265 const LogicVRegister& src2,
4271 T op2 = src2.Float<T>(i);
4304 const LogicVRegister& src2,
4307 fcmp<SimFloat16>(vform, dst, src1, src2, cond);
4309 fcmp<float>(vform, dst, src1, src2, cond);
4312 fcmp<double>(vform, dst, src1, src2, cond);
4342 const LogicVRegister& src2,
4347 LogicVRegister abs_src2 = fabs_<SimFloat16>(vform, temp2, src2);
4351 LogicVRegister abs_src2 = fabs_<float>(vform, temp2, src2);
4356 LogicVRegister abs_src2 = fabs_<double>(vform, temp2, src2);
4367 const LogicVRegister& src2) {
4371 T op2 = src2.Float<T>(i);
4383 const LogicVRegister& src2) {
4385 fmla<SimFloat16>(vform, dst, src1, src2);
4387 fmla<float>(vform, dst, src1, src2);
4390 fmla<double>(vform, dst, src1, src2);
4400 const LogicVRegister& src2) {
4404 T op2 = src2.Float<T>(i);
4416 const LogicVRegister& src2) {
4418 fmls<SimFloat16>(vform, dst, src1, src2);
4420 fmls<float>(vform, dst, src1, src2);
4423 fmls<double>(vform, dst, src1, src2);
4492 const LogicVRegister& src2) {
4494 fsub(vform, temp, src1, src2);
4529 const LogicVRegister& src2) { \
4531 uzp1(vform, temp1, src1, src2
4532 uzp2(vform, temp2, src1, src2); \
4634 const LogicVRegister& src2,
4639 LogicVRegister index_reg = dup_element(kFormat8H, temp, src2, index);
4642 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
4646 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index);
4656 const LogicVRegister& src2,
4661 LogicVRegister index_reg = dup_element(kFormat8H, temp, src2, index);
4664 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
4668 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index);
4678 const LogicVRegister& src2,
4683 LogicVRegister index_reg = dup_element(kFormat8H, temp, src2, index);
4686 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
4690 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index);
4700 const LogicVRegister& src2,
4705 LogicVRegister index_reg = dup_element(kFormat8H, temp, src2, index);
4708 LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
4712 LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index);
