Lines Matching refs:in1
162 * Arguments : Inputs - in0, in1, in2, in3, pdst, stride
164 * Store word from 'in1' to (pdst + stride)
168 #define SW4(in0, in1, in2, in3, pdst, stride) do { \
172 SW(in1, ptmp); \
179 #define SW3(in0, in1, in2, pdst, stride) do { \
183 SW(in1, ptmp); \
188 #define SW2(in0, in1, pdst, stride) do { \
192 SW(in1, ptmp); \
196 * Arguments : Inputs - in0, in1, in2, in3, pdst, stride
198 * Store double word from 'in1' to (pdst + stride)
202 #define SD4(in0, in1, in2, in3, pdst, stride) do { \
206 SD(in1, ptmp); \
292 * Arguments : Inputs - in0, in1, pdst, stride
294 * Store 16 byte elements from 'in1' to (pdst + stride)
296 #define ST_B2(RTYPE, in0, in1, pdst, stride) do { \
298 ST_B(RTYPE, in1, pdst + stride); \
303 #define ST_B4(RTYPE, in0, in1, in2, in3, pdst, stride) do { \
304 ST_B2(RTYPE, in0, in1, pdst, stride); \
310 #define ST_B8(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
312 ST_B4(RTYPE, in0, in1, in2, in3, pdst, stride); \
318 * Arguments : Inputs - in0, in1, in2, in3, pdst, stride
320 * Store 4 word elements from 'in1' to (pdst + 1 * stride)
324 #define ST_W2(RTYPE, in0, in1, pdst, stride) do { \
326 ST_W(RTYPE, in1, pdst + stride); \
331 #define ST_W3(RTYPE, in0, in1, in2, pdst, stride) do { \
332 ST_W2(RTYPE, in0, in1, pdst, stride); \
338 #define ST_W4(RTYPE, in0, in1, in2, in3, pdst, stride) do { \
339 ST_W2(RTYPE, in0, in1, pdst, stride); \
346 * Arguments : Inputs - in0, in1, pdst, stride
348 * Store 8 halfword elements from 'in1' to (pdst + stride)
350 #define ST_H2(RTYPE, in0, in1, pdst, stride) do { \
352 ST_H(RTYPE, in1, pdst + stride); \
384 * Arguments : Inputs - in0, in1, pdst, stride
394 #define ST4x4_UB(in0, in1, idx0, idx1, idx2, idx3, pdst, stride) do { \
398 const uint32_t out2_m = __msa_copy_s_w((v4i32)in1, idx2); \
399 const uint32_t out3_m = __msa_copy_s_w((v4i32)in1, idx3); \
403 #define ST4x8_UB(in0, in1, pdst, stride) do { \
406 ST4x4_UB(in1, in1, 0, 1, 2, 3, pblk_4x8 + 4 * stride, stride); \
410 * Arguments : Inputs - in0, in1, slide_val
413 * Details : Byte elements from 'in1' vector are slid into 'in0' by
416 #define SLDI_B(RTYPE, in0, in1, slide_val) \
417 (RTYPE)__msa_sldi_b((v16i8)in0, (v16i8)in1, slide_val) \
424 * Arguments : Inputs - in0, in1, in2, in3, mask0, mask1
427 * Details : Byte elements from 'in0' & 'in1' are copied selectively to
430 #define VSHF_B(RTYPE, in0, in1, mask) \
431 (RTYPE)__msa_vshf_b((v16i8)mask, (v16i8)in1, (v16i8)in0)
438 #define VSHF_B2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1) do { \
439 out0 = VSHF_B(RTYPE, in0, in1, mask0); \
448 * Arguments : Inputs - in0, in1, in2, in3, mask0, mask1
451 * Details : halfword elements from 'in0' & 'in1' are copied selectively to
454 #define VSHF_H2(RTYPE, in0, in1, in2, in3, mask0, mask1, out0, out1) do { \
455 out0 = (RTYPE)__msa_vshf_h((v8i16)mask0, (v8i16)in1, (v8i16)in0); \
536 #define CLIP_SH2_0_255(in0, in1) do { \
538 CLIP_SH_0_255(in1); \
541 #define CLIP_SH4_0_255(in0, in1, in2, in3) do { \
542 CLIP_SH2_0_255(in0, in1); \
558 #define CLIP_UH2_0_255(in0, in1) do { \
560 CLIP_UH_0_255(in1); \
574 #define CLIP_SW4_0_255(in0, in1, in2, in3) do { \
576 CLIP_SW_0_255(in1); \
633 Arguments : Inputs - in0, in1
640 #define HADD_SH2(RTYPE, in0, in1, out0, out1) do { \
642 out1 = (RTYPE)__msa_hadd_s_w((v8i16)in1, (v8i16)in1); \
646 #define HADD_SH4(RTYPE, in0, in1, in2, in3, out0, out1, out2, out3) do { \
647 HADD_SH2(RTYPE, in0, in1, out0, out1); \
653 * Arguments : Inputs - in0, in1
660 #define HSUB_UB2(RTYPE, in0, in1, out0, out1) do { \
662 out1 = (RTYPE)__msa_hsub_u_h((v16u8)in1, (v16u8)in1); \
669 * Arguments : Inputs - in0, in1, in2, in3
674 #define INSERT_W2(RTYPE, in0, in1, out) do { \
676 out = (RTYPE)__msa_insert_w((v4i32)out, 1, in1); \
681 #define INSERT_W4(RTYPE, in0, in1, in2, in3, out) do { \
683 out = (RTYPE)__msa_insert_w((v4i32)out, 1, in1); \
692 * Arguments : Inputs - in0, in1
696 * Set element 1 in vector 'out' to GPR value specified in 'in1'
698 #define INSERT_D2(RTYPE, in0, in1, out) do { \
700 out = (RTYPE)__msa_insert_d((v2i64)out, 1, in1); \
706 * Arguments : Inputs - in0, in1, in2, in3
709 * Details : Even byte elements of 'in0' and 'in1' are interleaved
712 #define ILVEV_B2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
713 out0 = (RTYPE)__msa_ilvev_b((v16i8)in1, (v16i8)in0); \
723 * Arguments : Inputs - in0, in1, in2, in3
726 * Details : Odd byte elements of 'in0' and 'in1' are interleaved
729 #define ILVOD_B2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
730 out0 = (RTYPE)__msa_ilvod_b((v16i8)in1, (v16i8)in0); \
740 * Arguments : Inputs - in0, in1, in2, in3
743 * Details : Even halfword elements of 'in0' and 'in1' are interleaved
746 #define ILVEV_H2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
747 out0 = (RTYPE)__msa_ilvev_h((v8i16)in1, (v8i16)in0); \
756 * Arguments : Inputs - in0, in1, in2, in3
759 * Details : Odd halfword elements of 'in0' and 'in1' are interleaved
762 #define ILVOD_H2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
763 out0 = (RTYPE)__msa_ilvod_h((v8i16)in1, (v8i16)in0); \
772 * Arguments : Inputs - in0, in1, in2, in3
775 * Details : Even word elements of 'in0' and 'in1' are interleaved
778 #define ILVEV_W2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
779 out0 = (RTYPE)__msa_ilvev_w((v4i32)in1, (v4i32)in0); \
788 * Arguments : Inputs - in0, in1, in2, in3
791 * Details : Even word elements of 'in0' and 'in1' are interleaved
796 #define ILVEVOD_W2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
797 out0 = (RTYPE)__msa_ilvev_w((v4i32)in1, (v4i32)in0); \
806 * Arguments : Inputs - in0, in1, in2, in3
809 * Details : Even half-word elements of 'in0' and 'in1' are interleaved
814 #define ILVEVOD_H2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
815 out0 = (RTYPE)__msa_ilvev_h((v8i16)in1, (v8i16)in0); \
824 * Arguments : Inputs - in0, in1, in2, in3
827 * Details : Even double word elements of 'in0' and 'in1' are interleaved
830 #define ILVEV_D2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
831 out0 = (RTYPE)__msa_ilvev_d((v2i64)in1, (v2i64)in0); \
840 * Arguments : Inputs - in0, in1, in2, in3
843 * Details : Left half of byte elements of 'in0' and 'in1' are interleaved
846 #define ILVL_B2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
847 out0 = (RTYPE)__msa_ilvl_b((v16i8)in0, (v16i8)in1); \
857 * Arguments : Inputs - in0, in1, in2, in3
860 * Details : Right half of byte elements of 'in0' and 'in1' are interleaved
863 #define ILVR_B2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
864 out0 = (RTYPE)__msa_ilvr_b((v16i8)in0, (v16i8)in1); \
873 #define ILVR_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
875 ILVR_B2(RTYPE, in0, in1, in2, in3, out0, out1); \
885 * Arguments : Inputs - in0, in1, in2, in3
888 * Details : Right half of halfword elements of 'in0' and 'in1' are
891 #define ILVR_H2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
892 out0 = (RTYPE)__msa_ilvr_h((v8i16)in0, (v8i16)in1); \
899 #define ILVR_H4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
901 ILVR_H2(RTYPE, in0, in1, in2, in3, out0, out1); \
909 * Arguments : Inputs - in0, in1, in2, in3
912 * Details : Right half of double word elements of 'in0' and 'in1' are
915 #define ILVR_D2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
916 out0 = (RTYPE)__msa_ilvr_d((v2i64)in0, (v2i64)in1); \
923 #define ILVR_D4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
925 ILVR_D2(RTYPE, in0, in1, in2, in3, out0, out1); \
932 * Arguments : Inputs - in0, in1
935 * Details : Right half of byte elements from 'in0' and 'in1' are
938 #define ILVRL_B2(RTYPE, in0, in1, out0, out1) do { \
939 out0 = (RTYPE)__msa_ilvr_b((v16i8)in0, (v16i8)in1); \
940 out1 = (RTYPE)__msa_ilvl_b((v16i8)in0, (v16i8)in1); \
948 #define ILVRL_H2(RTYPE, in0, in1, out0, out1) do { \
949 out0 = (RTYPE)__msa_ilvr_h((v8i16)in0, (v8i16)in1); \
950 out1 = (RTYPE)__msa_ilvl_h((v8i16)in0, (v8i16)in1); \
958 #define ILVRL_W2(RTYPE, in0, in1, out0, out1) do { \
959 out0 = (RTYPE)__msa_ilvr_w((v4i32)in0, (v4i32)in1); \
960 out1 = (RTYPE)__msa_ilvl_w((v4i32)in0, (v4i32)in1); \
968 * Arguments : Inputs - in0, in1, in2, in3
972 * 'out0' & even byte elements of 'in1' are copied to the right
975 #define PCKEV_B2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
976 out0 = (RTYPE)__msa_pckev_b((v16i8)in0, (v16i8)in1); \
984 #define PCKEV_B4(RTYPE, in0, in1, in2, in3, in4, in5, in6, in7, \
986 PCKEV_B2(RTYPE, in0, in1, in2, in3, out0, out1); \
995 * Arguments : Inputs - in0, in1, in2, in3
999 * 'out0' & even halfword elements of 'in1' are copied to the
1002 #define PCKEV_H2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
1003 out0 = (RTYPE)__msa_pckev_h((v8i16)in0, (v8i16)in1); \
1012 * Arguments : Inputs - in0, in1, in2, in3
1016 * 'out0' & even word elements of 'in1' are copied to the
1019 #define PCKEV_W2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
1020 out0 = (RTYPE)__msa_pckev_w((v4i32)in0, (v4i32)in1); \
1029 * Arguments : Inputs - in0, in1, in2, in3
1033 * 'out0' & odd halfword elements of 'in1' are copied to the
1036 #define PCKOD_H2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
1037 out0 = (RTYPE)__msa_pckod_h((v8i16)in0, (v8i16)in1); \
1046 * Arguments : Inputs - in0, in1, shift
1052 #define SRAI_W2(RTYPE, in0, in1, shift_val) do { \
1054 in1 = (RTYPE)SRAI_W(in1, shift_val); \
1059 #define SRAI_W4(RTYPE, in0, in1, in2, in3, shift_val) do { \
1060 SRAI_W2(RTYPE, in0, in1, shift_val); \
1067 * Arguments : Inputs - in0, in1, shift
1073 #define SRAI_H2(RTYPE, in0, in1, shift_val) do { \
1075 in1 = (RTYPE)SRAI_H(in1, shift_val); \
1081 * Arguments : Inputs - in0, in1, shift
1087 #define SRARI_W2(RTYPE, in0, in1, shift) do { \
1089 in1 = (RTYPE)__msa_srari_w((v4i32)in1, shift); \
1093 #define SRARI_W4(RTYPE, in0, in1, in2, in3, shift) do { \
1094 SRARI_W2(RTYPE, in0, in1, shift); \
1102 * Arguments : Inputs - in0, in1, shift
1111 #define SRAR_D2(RTYPE, in0, in1, shift) do { \
1113 in1 = (RTYPE)__msa_srar_d((v2i64)in1, (v2i64)shift); \
1119 #define SRAR_D4(RTYPE, in0, in1, in2, in3, shift) do { \
1120 SRAR_D2(RTYPE, in0, in1, shift); \
1127 * Arguments : Inputs - in0, in1, in2, in3
1129 * Details : Each element in 'in0' is added to 'in1' and result is written
1132 #define ADDVI_H2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
1133 out0 = (RTYPE)ADDVI_H(in0, in1); \
1140 * Arguments : Inputs - in0, in1, in2, in3
1142 * Details : Each element in 'in0' is added to 'in1' and result is written
1145 #define ADDVI_W2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
1146 out0 = (RTYPE)ADDVI_W(in0, in1); \
1152 * Arguments : Inputs - in0, in1
1155 * GP register in1 is replicated in each word element of out1
1157 #define FILL_W2(RTYPE, in0, in1, out0, out1) do { \
1159 out1 = (RTYPE)__msa_fill_w(in1); \
1164 * Arguments : Inputs - in0, in1, in2, in3
1166 * Details : Each element in 'in0' is added to 'in1' and result is written
1169 #define ADD2(in0, in1, in2, in3, out0, out1) do { \
1170 out0 = in0 + in1; \
1174 #define ADD4(in0, in1, in2, in3, in4, in5, in6, in7, \
1176 ADD2(in0, in1, in2, in3, out0, out1); \
1181 * Arguments : Inputs - in0, in1, in2, in3
1183 * Details : Each element in 'in1' is subtracted from 'in0' and result is
1186 #define SUB2(in0, in1, in2, in3, out0, out1) do { \
1187 out0 = in0 - in1; \
1191 #define SUB3(in0, in1, in2, in3, in4, in5, out0, out1, out2) do { \
1192 out0 = in0 - in1; \
1197 #define SUB4(in0, in1, in2, in3, in4, in5, in6, in7, \
1199 out0 = in0 - in1; \
1206 * Arguments : Inputs - in0, in1
1208 * Details : Each element in 'in1' is added to 'in0' and result is
1210 * Each element in 'in1' is subtracted from 'in0' and result is
1213 #define ADDSUB2(in0, in1, out0, out1) do { \
1214 out0 = in0 + in1; \
1215 out1 = in0 - in1; \
1219 * Arguments : Inputs - in0, in1, in2, in3
1221 * Details : Each element from 'in0' is multiplied with elements from 'in1'
1224 #define MUL2(in0, in1, in2, in3, out0, out1) do { \
1225 out0 = in0 * in1; \
1229 #define MUL4(in0, in1, in2, in3, in4, in5, in6, in7, \
1231 MUL2(in0, in1, in2, in3, out0, out1); \
1265 * Arguments : Inputs - in0, in1, in2, in3
1269 #define BUTTERFLY_4(in0, in1, in2, in3, out0, out1, out2, out3) do { \
1271 out1 = in1 + in2; \
1272 out2 = in1 - in2; \
1277 * Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7,
1282 #define TRANSPOSE16x4_UB_UB(in0, in1, in2, in3, in4, in5, in6, in7, \
1287 ILVEV_W2_SD(in1, in5, in9, in13, tmp0_m, tmp1_m); \
1299 * Arguments : Inputs - in0, in1, in2, in3, in4, in5, in6, in7,
1304 #define TRANSPOSE16x8_UB_UB(in0, in1, in2, in3, in4, in5, in6, in7, \
1310 ILVEV_D2_UB(in0, in8, in1, in9, out7, out6); \
1329 * Arguments : Inputs - in0, in1, in2, in3
1333 #define TRANSPOSE4x4_W(RTYPE, in0, in1, in2, in3, \
1336 ILVRL_W2_SW(in1, in0, s0_m, s1_m); \
1346 * Arguments : Inputs - in0, in1, in2, in3, pdst, stride
1350 #define ADDBLK_ST4x4_UB(in0, in1, in2, in3, pdst, stride) do { \
1356 ILVR_D2_SH(in1, in0, in3, in2, inp0_m, inp1_m); \
1370 * Arguments : Inputs - in0, in1, in2, in3, pdst, stride
1372 #define PCKEV_ST4x4_UB(in0, in1, in2, in3, pdst, stride) do { \
1374 PCKEV_B2_SB(in1, in0, in3, in2, tmp0_m, tmp1_m); \
1378 /* Description : average with rounding (in0 + in1 + 1) / 2.
1379 * Arguments : Inputs - in0, in1, in2, in3,
1383 * each unsigned byte element from 'in1' vector. Then the average
1386 #define AVER_UB2(RTYPE, in0, in1, in2, in3, out0, out1) do { \
1387 out0 = (RTYPE)__msa_aver_u_b((v16u8)in0, (v16u8)in1); \
