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      1 //===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file provides AArch64 specific target descriptions.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
     15 #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
     16 
     17 #include "llvm/Support/DataTypes.h"
     18 
     19 #include <memory>
     20 
     21 namespace llvm {
     22 class formatted_raw_ostream;
     23 class MCAsmBackend;
     24 class MCCodeEmitter;
     25 class MCContext;
     26 class MCInstrInfo;
     27 class MCInstPrinter;
     28 class MCRegisterInfo;
     29 class MCObjectTargetWriter;
     30 class MCStreamer;
     31 class MCSubtargetInfo;
     32 class MCTargetOptions;
     33 class MCTargetStreamer;
     34 class StringRef;
     35 class Target;
     36 class Triple;
     37 class raw_ostream;
     38 class raw_pwrite_stream;
     39 
     40 Target &getTheAArch64leTarget();
     41 Target &getTheAArch64beTarget();
     42 Target &getTheARM64Target();
     43 
     44 MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
     45                                           const MCRegisterInfo &MRI,
     46                                           MCContext &Ctx);
     47 MCAsmBackend *createAArch64leAsmBackend(const Target &T,
     48                                         const MCSubtargetInfo &STI,
     49                                         const MCRegisterInfo &MRI,
     50                                         const MCTargetOptions &Options);
     51 MCAsmBackend *createAArch64beAsmBackend(const Target &T,
     52                                         const MCSubtargetInfo &STI,
     53                                         const MCRegisterInfo &MRI,
     54                                         const MCTargetOptions &Options);
     55 
     56 std::unique_ptr<MCObjectTargetWriter>
     57 createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
     58 
     59 std::unique_ptr<MCObjectTargetWriter>
     60 createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype);
     61 
     62 std::unique_ptr<MCObjectTargetWriter> createAArch64WinCOFFObjectWriter();
     63 
     64 MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S,
     65                                                  formatted_raw_ostream &OS,
     66                                                  MCInstPrinter *InstPrint,
     67                                                  bool isVerboseAsm);
     68 
     69 MCTargetStreamer *createAArch64ObjectTargetStreamer(MCStreamer &S,
     70                                                     const MCSubtargetInfo &STI);
     71 
     72 namespace AArch64_MC {
     73 void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
     74 }
     75 
     76 } // End llvm namespace
     77 
     78 // Defines symbolic names for AArch64 registers.  This defines a mapping from
     79 // register name to register number.
     80 //
     81 #define GET_REGINFO_ENUM
     82 #include "AArch64GenRegisterInfo.inc"
     83 
     84 // Defines symbolic names for the AArch64 instructions.
     85 //
     86 #define GET_INSTRINFO_ENUM
     87 #include "AArch64GenInstrInfo.inc"
     88 
     89 #define GET_SUBTARGETINFO_ENUM
     90 #include "AArch64GenSubtargetInfo.inc"
     91 
     92 #endif
     93