1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige (at) armadeus.org> 4 */ 5 6 #ifndef __APF27_H 7 #define __APF27_H 8 9 /* FPGA program pin configuration */ 10 #define ACFG_FPGA_PWR (GPIO_PORTF | 19) /* FPGA prog pin */ 11 #define ACFG_FPGA_PRG (GPIO_PORTF | 11) /* FPGA prog pin */ 12 #define ACFG_FPGA_CLK (GPIO_PORTF | 15) /* FPGA clk pin */ 13 #define ACFG_FPGA_RDATA 0xD6000000 /* FPGA data addr */ 14 #define ACFG_FPGA_WDATA 0xD6000000 /* FPGA data addr */ 15 #define ACFG_FPGA_INIT (GPIO_PORTF | 12) /* FPGA init pin */ 16 #define ACFG_FPGA_DONE (GPIO_PORTF | 9) /* FPGA done pin */ 17 #define ACFG_FPGA_RW (GPIO_PORTF | 21) /* FPGA done pin */ 18 #define ACFG_FPGA_CS (GPIO_PORTF | 22) /* FPGA done pin */ 19 #define ACFG_FPGA_SUSPEND (GPIO_PORTF | 10) /* FPGA done pin */ 20 #define ACFG_FPGA_RESET (GPIO_PORTF | 7) /* FPGA done pin */ 21 22 /* MMC pin */ 23 #define PC_PWRON (GPIO_PORTF | 16) 24 25 /* 26 * MPU CLOCK source before PLL 27 * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ) 28 */ 29 #define ACFG_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */ 30 #define ACFG_MPCTL1_VAL 0 31 #define CONFIG_MPLL_FREQ 399 32 33 #define ACFG_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */ 34 35 /* Serial clock source before PLL (should be named ACFG_SYSPLL_CLK_FREQ)*/ 36 #define ACFG_SPCTL0_VAL 0x0475206F /* 299.99937 MHz */ 37 #define ACFG_SPCTL1_VAL 0 38 #define CONFIG_SPLL_FREQ 300 /* MHz */ 39 40 /* ARM bus frequency (have to be a CONFIG_MPLL_FREQ ratio) */ 41 #define CONFIG_ARM_FREQ 399 /* up to 400 MHz */ 42 43 /* external bus frequency (have to be a ACFG_CLK_FREQ ratio) */ 44 #define CONFIG_HCLK_FREQ 133 /* (ACFG_CLK_FREQ/2) */ 45 46 #define CONFIG_PERIF1_FREQ 16 /* 16.625 MHz UART, GPT, PWM */ 47 #define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC */ 48 #define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD */ 49 #define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI */ 50 #define CONFIG_SSI1_FREQ 66 /* 66.50 MHz SSI1 */ 51 #define CONFIG_SSI2_FREQ 66 /* 66.50 MHz SSI2 */ 52 #define CONFIG_MSHC_FREQ 66 /* 66.50 MHz MSHC */ 53 #define CONFIG_H264_FREQ 66 /* 66.50 MHz H264 */ 54 #define CONFIG_CLK0_DIV 3 /* Divide CLK0 by 4 */ 55 #define CONFIG_CLK0_EN 1 /* CLK0 enabled */ 56 57 /* external bus frequency (have to be a CONFIG_HCLK_FREQ ratio) */ 58 #define CONFIG_NFC_FREQ 44 /* NFC Clock up to 44 MHz wh 133MHz */ 59 60 /* external serial bus frequency (have to be a CONFIG_SPLL_FREQ ratio) */ 61 #define CONFIG_USB_FREQ 60 /* 60 MHz */ 62 63 /* 64 * SDRAM 65 */ 66 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ 67 /* micron 64MB */ 68 #define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 69 * column address bits 70 */ 71 #define ACFG_SDRAM_NUM_ROW 13 /* 11, 12 or 13 72 * row address bits 73 */ 74 #define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 75 * 2=4096 3=8192 refresh 76 */ 77 #define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power 78 * down delay 79 */ 80 #define ACFG_SDRAM_W2R_DELAY 1 /* write to read 81 * cycle delay > 0 82 */ 83 #define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ 84 #define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register 85 * cycle delay 1..4 86 */ 87 #define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck 88 * SDRAM: 0=1ck 1=2ck 89 */ 90 #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ 91 #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ 92 #define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ 93 #define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC 94 * refresh to command) 95 */ 96 #define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time 97 * estimated fo CL=1 98 * 0=force 3 for lpddr 99 */ 100 #define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater 101 * 3=Eighth 4=Sixteenth 102 */ 103 #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half 104 * 2=quater 3=Eighth 105 */ 106 #define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ 107 #define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access 108 * 0 = Burst mode 109 */ 110 #endif 111 112 #if (ACFG_SDRAM_MBYTE_SYZE == 128) 113 /* micron 128MB */ 114 #define ACFG_SDRAM_NUM_COL 9 /* 8, 9, 10 or 11 115 * column address bits 116 */ 117 #define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13 118 * row address bits 119 */ 120 #define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 121 * 2=4096 3=8192 refresh 122 */ 123 #define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power 124 * down delay 125 */ 126 #define ACFG_SDRAM_W2R_DELAY 1 /* write to read 127 * cycle delay > 0 128 */ 129 #define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ 130 #define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register 131 * cycle delay 1..4 132 */ 133 #define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck 134 * SDRAM: 0=1ck 1=2ck 135 */ 136 #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ 137 #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ 138 #define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ 139 #define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC 140 * refresh to command) 141 */ 142 #define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time 143 * estimated fo CL=1 144 * 0=force 3 for lpddr 145 */ 146 #define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater 147 * 3=Eighth 4=Sixteenth 148 */ 149 #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 1=half 150 * 2=quater 3=Eighth 151 */ 152 #define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ 153 #define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access 154 * 0 = Burst mode 155 */ 156 #endif 157 158 #if (ACFG_SDRAM_MBYTE_SYZE == 256) 159 /* micron 256MB */ 160 #define ACFG_SDRAM_NUM_COL 10 /* 8, 9, 10 or 11 161 * column address bits 162 */ 163 #define ACFG_SDRAM_NUM_ROW 14 /* 11, 12 or 13 164 * row address bits 165 */ 166 #define ACFG_SDRAM_REFRESH 3 /* 0=OFF 1=2048 167 * 2=4096 3=8192 refresh 168 */ 169 #define ACFG_SDRAM_EXIT_PWD 25 /* ns exit power 170 * down delay 171 */ 172 #define ACFG_SDRAM_W2R_DELAY 1 /* write to read cycle 173 * delay > 0 174 */ 175 #define ACFG_SDRAM_ROW_PRECHARGE_DELAY 18 /* ns */ 176 #define ACFG_SDRAM_TMRD_DELAY 2 /* Load mode register 177 * cycle delay 1..4 178 */ 179 #define ACFG_SDRAM_TWR_DELAY 1 /* LPDDR: 0=2ck 1=3ck 180 * SDRAM: 0=1ck 1=2ck 181 */ 182 #define ACFG_SDRAM_RAS_DELAY 42 /* ns ACTIVE-to-PRECHARGE delay */ 183 #define ACFG_SDRAM_RRD_DELAY 12 /* ns ACTIVE-to-ACTIVE delay */ 184 #define ACFG_SDRAM_RCD_DELAY 18 /* ns Row to Column delay */ 185 #define ACFG_SDRAM_RC_DELAY 70 /* ns Row cycle delay (tRFC 186 * refresh to command) 187 */ 188 #define ACFG_SDRAM_CLOCK_CYCLE_CL_1 0 /* ns clock cycle time 189 * estimated fo CL=1 190 * 0=force 3 for lpddr 191 */ 192 #define ACFG_SDRAM_PARTIAL_ARRAY_SR 0 /* 0=full 1=half 2=quater 193 * 3=Eighth 4=Sixteenth 194 */ 195 #define ACFG_SDRAM_DRIVE_STRENGH 0 /* 0=Full-strength 196 * 1=half 197 * 2=quater 198 * 3=Eighth 199 */ 200 #define ACFG_SDRAM_BURST_LENGTH 3 /* 2^N BYTES (N=0..3) */ 201 #define ACFG_SDRAM_SINGLE_ACCESS 0 /* 1= single access 202 * 0 = Burst mode 203 */ 204 #endif 205 206 /* 207 * External interface 208 */ 209 /* 210 * CSCRxU_VAL: 211 * 31| x | x | x x |x x x x| x x | x | x |x x x x|16 212 * |SP |WP | BCD | BCS | PSZ |PME|SYNC| DOL | 213 * 214 * 15| x x | x x x x x x | x | x x x x | x x x x |0 215 * | CNC | WSC |EW | WWS | EDC | 216 * 217 * CSCRxL_VAL: 218 * 31| x x x x | x x x x | x x x x | x x x x |16 219 * | OEA | OEN | EBWA | EBWN | 220 * 15|x x x x| x |x x x |x x x x| x | x | x | x | 0 221 * | CSA |EBC| DSZ | CSN |PSR|CRE|WRAP|CSEN| 222 * 223 * CSCRxA_VAL: 224 * 31| x x x x | x x x x | x x x x | x x x x |16 225 * | EBRA | EBRN | RWA | RWN | 226 * 15| x | x x |x x x|x x|x x|x x| x | x | x | x | 0 227 * |MUM| LAH | LBN |LBA|DWW|DCT|WWU|AGE|CNC2|FCE| 228 */ 229 230 /* CS0 configuration for 16 bit nor flash */ 231 #define ACFG_CS0U_VAL 0x0000CC03 232 #define ACFG_CS0L_VAL 0xa0330D01 233 #define ACFG_CS0A_VAL 0x00220800 234 235 #define ACFG_CS1U_VAL 0x00000f00 236 #define ACFG_CS1L_VAL 0x00000D01 237 #define ACFG_CS1A_VAL 0 238 239 #define ACFG_CS2U_VAL 0 240 #define ACFG_CS2L_VAL 0 241 #define ACFG_CS2A_VAL 0 242 243 #define ACFG_CS3U_VAL 0 244 #define ACFG_CS3L_VAL 0 245 #define ACFG_CS3A_VAL 0 246 247 #define ACFG_CS4U_VAL 0 248 #define ACFG_CS4L_VAL 0 249 #define ACFG_CS4A_VAL 0 250 251 /* FPGA 16 bit data bus */ 252 #define ACFG_CS5U_VAL 0x00000600 253 #define ACFG_CS5L_VAL 0x00000D01 254 #define ACFG_CS5A_VAL 0 255 256 #define ACFG_EIM_VAL 0x00002200 257 258 259 /* 260 * FPGA specific settings 261 */ 262 263 /* CLKO */ 264 #define ACFG_CCSR_VAL 0x00000305 265 /* drive strength CLKO set to 2 */ 266 #define ACFG_DSCR10_VAL 0x00020000 267 /* drive strength A1..A12 set to 2 */ 268 #define ACFG_DSCR3_VAL 0x02AAAAA8 269 /* drive strength ctrl */ 270 #define ACFG_DSCR7_VAL 0x00020880 271 /* drive strength data */ 272 #define ACFG_DSCR2_VAL 0xAAAAAAAA 273 274 275 /* 276 * Default configuration for GPIOs and peripherals 277 */ 278 #define ACFG_DDIR_A_VAL 0x00000000 279 #define ACFG_OCR1_A_VAL 0x00000000 280 #define ACFG_OCR2_A_VAL 0x00000000 281 #define ACFG_ICFA1_A_VAL 0xFFFFFFFF 282 #define ACFG_ICFA2_A_VAL 0xFFFFFFFF 283 #define ACFG_ICFB1_A_VAL 0xFFFFFFFF 284 #define ACFG_ICFB2_A_VAL 0xFFFFFFFF 285 #define ACFG_DR_A_VAL 0x00000000 286 #define ACFG_GIUS_A_VAL 0xFFFFFFFF 287 #define ACFG_ICR1_A_VAL 0x00000000 288 #define ACFG_ICR2_A_VAL 0x00000000 289 #define ACFG_IMR_A_VAL 0x00000000 290 #define ACFG_GPR_A_VAL 0x00000000 291 #define ACFG_PUEN_A_VAL 0xFFFFFFFF 292 293 #define ACFG_DDIR_B_VAL 0x00000000 294 #define ACFG_OCR1_B_VAL 0x00000000 295 #define ACFG_OCR2_B_VAL 0x00000000 296 #define ACFG_ICFA1_B_VAL 0xFFFFFFFF 297 #define ACFG_ICFA2_B_VAL 0xFFFFFFFF 298 #define ACFG_ICFB1_B_VAL 0xFFFFFFFF 299 #define ACFG_ICFB2_B_VAL 0xFFFFFFFF 300 #define ACFG_DR_B_VAL 0x00000000 301 #define ACFG_GIUS_B_VAL 0xFF3FFFF0 302 #define ACFG_ICR1_B_VAL 0x00000000 303 #define ACFG_ICR2_B_VAL 0x00000000 304 #define ACFG_IMR_B_VAL 0x00000000 305 #define ACFG_GPR_B_VAL 0x00000000 306 #define ACFG_PUEN_B_VAL 0xFFFFFFFF 307 308 #define ACFG_DDIR_C_VAL 0x00000000 309 #define ACFG_OCR1_C_VAL 0x00000000 310 #define ACFG_OCR2_C_VAL 0x00000000 311 #define ACFG_ICFA1_C_VAL 0xFFFFFFFF 312 #define ACFG_ICFA2_C_VAL 0xFFFFFFFF 313 #define ACFG_ICFB1_C_VAL 0xFFFFFFFF 314 #define ACFG_ICFB2_C_VAL 0xFFFFFFFF 315 #define ACFG_DR_C_VAL 0x00000000 316 #define ACFG_GIUS_C_VAL 0xFFFFC07F 317 #define ACFG_ICR1_C_VAL 0x00000000 318 #define ACFG_ICR2_C_VAL 0x00000000 319 #define ACFG_IMR_C_VAL 0x00000000 320 #define ACFG_GPR_C_VAL 0x00000000 321 #define ACFG_PUEN_C_VAL 0xFFFFFF87 322 323 #define ACFG_DDIR_D_VAL 0x00000000 324 #define ACFG_OCR1_D_VAL 0x00000000 325 #define ACFG_OCR2_D_VAL 0x00000000 326 #define ACFG_ICFA1_D_VAL 0xFFFFFFFF 327 #define ACFG_ICFA2_D_VAL 0xFFFFFFFF 328 #define ACFG_ICFB1_D_VAL 0xFFFFFFFF 329 #define ACFG_ICFB2_D_VAL 0xFFFFFFFF 330 #define ACFG_DR_D_VAL 0x00000000 331 #define ACFG_GIUS_D_VAL 0xFFFFFFFF 332 #define ACFG_ICR1_D_VAL 0x00000000 333 #define ACFG_ICR2_D_VAL 0x00000000 334 #define ACFG_IMR_D_VAL 0x00000000 335 #define ACFG_GPR_D_VAL 0x00000000 336 #define ACFG_PUEN_D_VAL 0xFFFFFFFF 337 338 #define ACFG_DDIR_E_VAL 0x00000000 339 #define ACFG_OCR1_E_VAL 0x00000000 340 #define ACFG_OCR2_E_VAL 0x00000000 341 #define ACFG_ICFA1_E_VAL 0xFFFFFFFF 342 #define ACFG_ICFA2_E_VAL 0xFFFFFFFF 343 #define ACFG_ICFB1_E_VAL 0xFFFFFFFF 344 #define ACFG_ICFB2_E_VAL 0xFFFFFFFF 345 #define ACFG_DR_E_VAL 0x00000000 346 #define ACFG_GIUS_E_VAL 0xFCFFCCF8 347 #define ACFG_ICR1_E_VAL 0x00000000 348 #define ACFG_ICR2_E_VAL 0x00000000 349 #define ACFG_IMR_E_VAL 0x00000000 350 #define ACFG_GPR_E_VAL 0x00000000 351 #define ACFG_PUEN_E_VAL 0xFFFFFFFF 352 353 #define ACFG_DDIR_F_VAL 0x00000000 354 #define ACFG_OCR1_F_VAL 0x00000000 355 #define ACFG_OCR2_F_VAL 0x00000000 356 #define ACFG_ICFA1_F_VAL 0xFFFFFFFF 357 #define ACFG_ICFA2_F_VAL 0xFFFFFFFF 358 #define ACFG_ICFB1_F_VAL 0xFFFFFFFF 359 #define ACFG_ICFB2_F_VAL 0xFFFFFFFF 360 #define ACFG_DR_F_VAL 0x00000000 361 #define ACFG_GIUS_F_VAL 0xFF7F8000 362 #define ACFG_ICR1_F_VAL 0x00000000 363 #define ACFG_ICR2_F_VAL 0x00000000 364 #define ACFG_IMR_F_VAL 0x00000000 365 #define ACFG_GPR_F_VAL 0x00000000 366 #define ACFG_PUEN_F_VAL 0xFFFFFFFF 367 368 /* Enforce DDR signal strengh & enable USB/PP/DMA burst override bits */ 369 #define ACFG_GPCR_VAL 0x0003000F 370 371 #define ACFG_ESDMISC_VAL ESDMISC_LHD+ESDMISC_MDDREN 372 373 /* FMCR select num LPDDR RAMs and nand 16bits, 2KB pages */ 374 #if (CONFIG_NR_DRAM_BANKS == 1) 375 #define ACFG_FMCR_VAL 0xFFFFFFF9 376 #elif (CONFIG_NR_DRAM_BANKS == 2) 377 #define ACFG_FMCR_VAL 0xFFFFFFFB 378 #endif 379 380 #define ACFG_AIPI1_PSR0_VAL 0x20040304 381 #define ACFG_AIPI1_PSR1_VAL 0xDFFBFCFB 382 #define ACFG_AIPI2_PSR0_VAL 0x00000000 383 #define ACFG_AIPI2_PSR1_VAL 0xFFFFFFFF 384 385 /* PCCR enable DMA FEC I2C1 IIM SDHC1 */ 386 #define ACFG_PCCR0_VAL 0x05070410 387 #define ACFG_PCCR1_VAL 0xA14A0608 388 389 /* 390 * From here, there should not be any user configuration. 391 * All Equations are automatic 392 */ 393 394 /* fixme none integer value (7.5ns) => 2*hclock = 15ns */ 395 #define ACFG_2XHCLK_LGTH (2000/CONFIG_HCLK_FREQ) /* ns */ 396 397 /* USB 60 MHz ; ARM up to 400; HClK up to 133MHz*/ 398 #define CSCR_MASK 0x0300800D 399 400 #define ACFG_CSCR_VAL \ 401 (CSCR_MASK \ 402 |((((CONFIG_SPLL_FREQ/CONFIG_USB_FREQ)-1)&0x07) << 28) \ 403 |((((CONFIG_MPLL_FREQ/CONFIG_ARM_FREQ)-1)&0x03) << 12) \ 404 |((((ACFG_CLK_FREQ/CONFIG_HCLK_FREQ)-1)&0x03) << 8)) 405 406 /* SSIx CLKO NFC H264 MSHC */ 407 #define ACFG_PCDR0_VAL\ 408 (((((ACFG_CLK_FREQ/CONFIG_MSHC_FREQ)-1)&0x3F)<<0) \ 409 |((((CONFIG_HCLK_FREQ/CONFIG_NFC_FREQ)-1)&0x0F)<<6) \ 410 |(((((ACFG_CLK_FREQ/CONFIG_H264_FREQ)-2)*2)&0x3F)<<10)\ 411 |(((((ACFG_CLK_FREQ/CONFIG_SSI1_FREQ)-2)*2)&0x3F)<<16)\ 412 |(((CONFIG_CLK0_DIV)&0x07)<<22)\ 413 |(((CONFIG_CLK0_EN)&0x01)<<25)\ 414 |(((((ACFG_CLK_FREQ/CONFIG_SSI2_FREQ)-2)*2)&0x3F)<<26)) 415 416 /* PERCLKx */ 417 #define ACFG_PCDR1_VAL\ 418 (((((ACFG_CLK_FREQ/CONFIG_PERIF1_FREQ)-1)&0x3F)<<0) \ 419 |((((ACFG_CLK_FREQ/CONFIG_PERIF2_FREQ)-1)&0x3F)<<8) \ 420 |((((ACFG_CLK_FREQ/CONFIG_PERIF3_FREQ)-1)&0x3F)<<16) \ 421 |((((ACFG_CLK_FREQ/CONFIG_PERIF4_FREQ)-1)&0x3F)<<24)) 422 423 /* SDRAM controller programming Values */ 424 #if (((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1) > (3*ACFG_2XHCLK_LGTH)) || \ 425 (ACFG_SDRAM_CLOCK_CYCLE_CL_1 < 1)) 426 #define REG_FIELD_SCL_VAL 3 427 #define REG_FIELD_SCLIMX_VAL 0 428 #else 429 #define REG_FIELD_SCL_VAL\ 430 ((2*ACFG_SDRAM_CLOCK_CYCLE_CL_1+ACFG_2XHCLK_LGTH-1)/ \ 431 ACFG_2XHCLK_LGTH) 432 #define REG_FIELD_SCLIMX_VAL REG_FIELD_SCL_VAL 433 #endif 434 435 #if ((2*ACFG_SDRAM_RC_DELAY) > (16*ACFG_2XHCLK_LGTH)) 436 #define REG_FIELD_SRC_VAL 0 437 #else 438 #define REG_FIELD_SRC_VAL\ 439 ((2*ACFG_SDRAM_RC_DELAY+ACFG_2XHCLK_LGTH-1)/ \ 440 ACFG_2XHCLK_LGTH) 441 #endif 442 443 /* TBD Power down timer ; PRCT Bit Field Encoding; burst length 8 ; FP = 0*/ 444 #define REG_ESDCTL_BASE_CONFIG (0x80020485\ 445 | (((ACFG_SDRAM_NUM_ROW-11)&0x7)<<24)\ 446 | (((ACFG_SDRAM_NUM_COL-8)&0x3)<<20)\ 447 | (((ACFG_SDRAM_REFRESH)&0x7)<<13)) 448 449 #define ACFG_NORMAL_RW_CMD ((0x0<<28)+REG_ESDCTL_BASE_CONFIG) 450 #define ACFG_PRECHARGE_CMD ((0x1<<28)+REG_ESDCTL_BASE_CONFIG) 451 #define ACFG_AUTOREFRESH_CMD ((0x2<<28)+REG_ESDCTL_BASE_CONFIG) 452 #define ACFG_SET_MODE_REG_CMD ((0x3<<28)+REG_ESDCTL_BASE_CONFIG) 453 454 /* ESDRAMC Configuration Registers : force CL=3 to lpddr */ 455 #define ACFG_SDRAM_ESDCFG_REGISTER_VAL (0x0\ 456 | (((((2*ACFG_SDRAM_EXIT_PWD+ACFG_2XHCLK_LGTH-1)/ \ 457 ACFG_2XHCLK_LGTH)-1)&0x3)<<21)\ 458 | (((ACFG_SDRAM_W2R_DELAY-1)&0x1)<<20)\ 459 | (((((2*ACFG_SDRAM_ROW_PRECHARGE_DELAY+ \ 460 ACFG_2XHCLK_LGTH-1)/ACFG_2XHCLK_LGTH)-1)&0x3)<<18) \ 461 | (((ACFG_SDRAM_TMRD_DELAY-1)&0x3)<<16)\ 462 | (((ACFG_SDRAM_TWR_DELAY)&0x1)<<15)\ 463 | (((((2*ACFG_SDRAM_RAS_DELAY+ACFG_2XHCLK_LGTH-1)/ \ 464 ACFG_2XHCLK_LGTH)-1)&0x7)<<12) \ 465 | (((((2*ACFG_SDRAM_RRD_DELAY+ACFG_2XHCLK_LGTH-1)/ \ 466 ACFG_2XHCLK_LGTH)-1)&0x3)<<10) \ 467 | (((REG_FIELD_SCLIMX_VAL)&0x3)<<8)\ 468 | (((((2*ACFG_SDRAM_RCD_DELAY+ACFG_2XHCLK_LGTH-1)/ \ 469 ACFG_2XHCLK_LGTH)-1)&0x7)<<4) \ 470 | (((REG_FIELD_SRC_VAL)&0x0F)<<0)) 471 472 /* Issue Mode register Command to SDRAM */ 473 #define ACFG_SDRAM_MODE_REGISTER_VAL\ 474 ((((ACFG_SDRAM_BURST_LENGTH)&0x7)<<(0))\ 475 | (((REG_FIELD_SCL_VAL)&0x7)<<(4))\ 476 | ((0)<<(3)) /* sequentiql access */ \ 477 /*| (((ACFG_SDRAM_SINGLE_ACCESS)&0x1)<<(1))*/) 478 479 /* Issue Extended Mode register Command to SDRAM */ 480 #define ACFG_SDRAM_EXT_MODE_REGISTER_VAL\ 481 ((ACFG_SDRAM_PARTIAL_ARRAY_SR<<0)\ 482 | (ACFG_SDRAM_DRIVE_STRENGH<<(5))\ 483 | (1<<(ACFG_SDRAM_NUM_COL+ACFG_SDRAM_NUM_ROW+1+2))) 484 485 /* Issue Precharge all Command to SDRAM */ 486 #define ACFG_SDRAM_PRECHARGE_ALL_VAL (1<<10) 487 488 #endif /* __APF27_H */ 489
