1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2010 4 * Texas Instruments, <www.ti.com> 5 * 6 * Aneesh V <aneesh (at) ti.com> 7 */ 8 #ifndef _CLOCKS_OMAP4_H_ 9 #define _CLOCKS_OMAP4_H_ 10 #include <common.h> 11 #include <asm/omap_common.h> 12 13 /* 14 * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per 15 * loop, allow for a minimum of 2 ms wait (in reality the wait will be 16 * much more than that) 17 */ 18 #define LDELAY 1000000 19 20 /* CM_DLL_CTRL */ 21 #define CM_DLL_CTRL_OVERRIDE_SHIFT 0 22 #define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) 23 #define CM_DLL_CTRL_NO_OVERRIDE 0 24 25 /* CM_CLKMODE_DPLL */ 26 #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 27 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) 28 #define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10 29 #define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10) 30 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9 31 #define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9) 32 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8 33 #define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8) 34 #define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5 35 #define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5) 36 #define CM_CLKMODE_DPLL_EN_SHIFT 0 37 #define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0) 38 39 #define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0 40 #define CM_CLKMODE_DPLL_DPLL_EN_MASK 7 41 42 #define DPLL_EN_STOP 1 43 #define DPLL_EN_MN_BYPASS 4 44 #define DPLL_EN_LOW_POWER_BYPASS 5 45 #define DPLL_EN_FAST_RELOCK_BYPASS 6 46 #define DPLL_EN_LOCK 7 47 48 /* CM_IDLEST_DPLL fields */ 49 #define ST_DPLL_CLK_MASK 1 50 51 /* CM_CLKSEL_DPLL */ 52 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24 53 #define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24) 54 #define CM_CLKSEL_DPLL_M_SHIFT 8 55 #define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8) 56 #define CM_CLKSEL_DPLL_N_SHIFT 0 57 #define CM_CLKSEL_DPLL_N_MASK 0x7F 58 #define CM_CLKSEL_DCC_EN_SHIFT 22 59 #define CM_CLKSEL_DCC_EN_MASK (1 << 22) 60 61 /* CM_SYS_CLKSEL */ 62 #define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 63 64 /* CM_CLKSEL_CORE */ 65 #define CLKSEL_CORE_SHIFT 0 66 #define CLKSEL_L3_SHIFT 4 67 #define CLKSEL_L4_SHIFT 8 68 69 #define CLKSEL_CORE_X2_DIV_1 0 70 #define CLKSEL_L3_CORE_DIV_2 1 71 #define CLKSEL_L4_L3_DIV_2 1 72 73 /* CM_ABE_PLL_REF_CLKSEL */ 74 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0 75 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1 76 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0 77 #define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1 78 79 /* CM_BYPCLK_DPLL_IVA */ 80 #define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0 81 #define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3 82 83 #define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1 84 85 /* CM_SHADOW_FREQ_CONFIG1 */ 86 #define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1 87 #define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4 88 #define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8 89 90 #define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8 91 #define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8) 92 93 #define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11 94 #define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11) 95 96 /*CM_<clock_domain>__CLKCTRL */ 97 #define CD_CLKCTRL_CLKTRCTRL_SHIFT 0 98 #define CD_CLKCTRL_CLKTRCTRL_MASK 3 99 100 #define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0 101 #define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1 102 #define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2 103 #define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3 104 105 106 /* CM_<clock_domain>_<module>_CLKCTRL */ 107 #define MODULE_CLKCTRL_MODULEMODE_SHIFT 0 108 #define MODULE_CLKCTRL_MODULEMODE_MASK 3 109 #define MODULE_CLKCTRL_IDLEST_SHIFT 16 110 #define MODULE_CLKCTRL_IDLEST_MASK (3 << 16) 111 112 #define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0 113 #define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1 114 #define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2 115 116 #define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0 117 #define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1 118 #define MODULE_CLKCTRL_IDLEST_IDLE 2 119 #define MODULE_CLKCTRL_IDLEST_DISABLED 3 120 121 /* CM_L4PER_GPIO4_CLKCTRL */ 122 #define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8) 123 124 /* CM_L3INIT_HSMMCn_CLKCTRL */ 125 #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) 126 127 /* CM_WKUP_GPTIMER1_CLKCTRL */ 128 #define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24) 129 130 /* CM_CAM_ISS_CLKCTRL */ 131 #define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8) 132 133 /* CM_DSS_DSS_CLKCTRL */ 134 #define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00 135 136 /* CM_COREAON_USB_PHY_CORE_CLKCTRL */ 137 #define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8) 138 139 /* CM_L3INIT_USBPHY_CLKCTRL */ 140 #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK (1 << 8) 141 142 /* CM_MPU_MPU_CLKCTRL */ 143 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24 144 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) 145 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 25 146 #define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) 147 148 /* Clock frequencies */ 149 #define OMAP_SYS_CLK_IND_38_4_MHZ 6 150 151 /* PRM_VC_VAL_BYPASS */ 152 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400 153 154 /* PMIC */ 155 #define SMPS_I2C_SLAVE_ADDR 0x12 156 /* TWL6030 SMPS */ 157 #define SMPS_REG_ADDR_VCORE1 0x55 158 #define SMPS_REG_ADDR_VCORE2 0x5B 159 #define SMPS_REG_ADDR_VCORE3 0x61 160 /* TWL6032 SMPS */ 161 #define SMPS_REG_ADDR_SMPS1 0x55 162 #define SMPS_REG_ADDR_SMPS2 0x5B 163 #define SMPS_REG_ADDR_SMPS5 0x49 164 165 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV 607700 166 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000 167 168 /* TPS */ 169 #define TPS62361_I2C_SLAVE_ADDR 0x60 170 #define TPS62361_REG_ADDR_SET0 0x0 171 #define TPS62361_REG_ADDR_SET1 0x1 172 #define TPS62361_REG_ADDR_SET2 0x2 173 #define TPS62361_REG_ADDR_SET3 0x3 174 #define TPS62361_REG_ADDR_CTRL 0x4 175 #define TPS62361_REG_ADDR_TEMP 0x5 176 #define TPS62361_REG_ADDR_RMP_CTRL 0x6 177 #define TPS62361_REG_ADDR_CHIP_ID 0x8 178 #define TPS62361_REG_ADDR_CHIP_ID_2 0x9 179 180 #define TPS62361_BASE_VOLT_MV 500 181 #define TPS62361_VSEL0_GPIO 7 182 183 /* AUXCLKx reg fields */ 184 #define AUXCLK_ENABLE_MASK (1 << 8) 185 #define AUXCLK_SRCSELECT_SHIFT 1 186 #define AUXCLK_SRCSELECT_MASK (3 << 1) 187 #define AUXCLK_CLKDIV_SHIFT 16 188 #define AUXCLK_CLKDIV_MASK (0xF << 16) 189 190 #define AUXCLK_SRCSELECT_SYS_CLK 0 191 #define AUXCLK_SRCSELECT_CORE_DPLL 1 192 #define AUXCLK_SRCSELECT_PER_DPLL 2 193 #define AUXCLK_SRCSELECT_ALTERNATE 3 194 195 #define AUXCLK_CLKDIV_2 1 196 #define AUXCLK_CLKDIV_16 0xF 197 198 /* ALTCLKSRC */ 199 #define ALTCLKSRC_MODE_MASK 3 200 #define ALTCLKSRC_ENABLE_INT_MASK 4 201 #define ALTCLKSRC_ENABLE_EXT_MASK 8 202 203 #define ALTCLKSRC_MODE_ACTIVE 1 204 205 #define DPLL_NO_LOCK 0 206 #define DPLL_LOCK 1 207 208 /* Clock Defines */ 209 #define V_OSCK 38400000 /* Clock output from T2 */ 210 #define V_SCLK V_OSCK 211 212 struct omap4_scrm_regs { 213 u32 revision; /* 0x0000 */ 214 u32 pad00[63]; 215 u32 clksetuptime; /* 0x0100 */ 216 u32 pmicsetuptime; /* 0x0104 */ 217 u32 pad01[2]; 218 u32 altclksrc; /* 0x0110 */ 219 u32 pad02[2]; 220 u32 c2cclkm; /* 0x011c */ 221 u32 pad03[56]; 222 u32 extclkreq; /* 0x0200 */ 223 u32 accclkreq; /* 0x0204 */ 224 u32 pwrreq; /* 0x0208 */ 225 u32 pad04[1]; 226 u32 auxclkreq0; /* 0x0210 */ 227 u32 auxclkreq1; /* 0x0214 */ 228 u32 auxclkreq2; /* 0x0218 */ 229 u32 auxclkreq3; /* 0x021c */ 230 u32 auxclkreq4; /* 0x0220 */ 231 u32 auxclkreq5; /* 0x0224 */ 232 u32 pad05[3]; 233 u32 c2cclkreq; /* 0x0234 */ 234 u32 pad06[54]; 235 u32 auxclk0; /* 0x0310 */ 236 u32 auxclk1; /* 0x0314 */ 237 u32 auxclk2; /* 0x0318 */ 238 u32 auxclk3; /* 0x031c */ 239 u32 auxclk4; /* 0x0320 */ 240 u32 auxclk5; /* 0x0324 */ 241 u32 pad07[54]; 242 u32 rsttime_reg; /* 0x0400 */ 243 u32 pad08[6]; 244 u32 c2crstctrl; /* 0x041c */ 245 u32 extpwronrstctrl; /* 0x0420 */ 246 u32 pad09[59]; 247 u32 extwarmrstst_reg; /* 0x0510 */ 248 u32 apewarmrstst_reg; /* 0x0514 */ 249 u32 pad10[1]; 250 u32 c2cwarmrstst_reg; /* 0x051C */ 251 }; 252 #endif /* _CLOCKS_OMAP4_H_ */ 253
