1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Freescale i.MX28 APBH Register Definitions 4 * 5 * Copyright (C) 2011 Marek Vasut <marek.vasut (at) gmail.com> 6 * on behalf of DENX Software Engineering GmbH 7 * 8 * Based on code from LTIB: 9 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. 10 */ 11 12 #ifndef __REGS_APBH_H__ 13 #define __REGS_APBH_H__ 14 15 #include <asm/mach-imx/regs-common.h> 16 17 #ifndef __ASSEMBLY__ 18 19 #if defined(CONFIG_MX23) 20 struct mxs_apbh_regs { 21 mxs_reg_32(hw_apbh_ctrl0) 22 mxs_reg_32(hw_apbh_ctrl1) 23 mxs_reg_32(hw_apbh_ctrl2) 24 mxs_reg_32(hw_apbh_channel_ctrl) 25 26 union { 27 struct { 28 mxs_reg_32(hw_apbh_ch_curcmdar) 29 mxs_reg_32(hw_apbh_ch_nxtcmdar) 30 mxs_reg_32(hw_apbh_ch_cmd) 31 mxs_reg_32(hw_apbh_ch_bar) 32 mxs_reg_32(hw_apbh_ch_sema) 33 mxs_reg_32(hw_apbh_ch_debug1) 34 mxs_reg_32(hw_apbh_ch_debug2) 35 } ch[8]; 36 struct { 37 mxs_reg_32(hw_apbh_ch0_curcmdar) 38 mxs_reg_32(hw_apbh_ch0_nxtcmdar) 39 mxs_reg_32(hw_apbh_ch0_cmd) 40 mxs_reg_32(hw_apbh_ch0_bar) 41 mxs_reg_32(hw_apbh_ch0_sema) 42 mxs_reg_32(hw_apbh_ch0_debug1) 43 mxs_reg_32(hw_apbh_ch0_debug2) 44 mxs_reg_32(hw_apbh_ch1_curcmdar) 45 mxs_reg_32(hw_apbh_ch1_nxtcmdar) 46 mxs_reg_32(hw_apbh_ch1_cmd) 47 mxs_reg_32(hw_apbh_ch1_bar) 48 mxs_reg_32(hw_apbh_ch1_sema) 49 mxs_reg_32(hw_apbh_ch1_debug1) 50 mxs_reg_32(hw_apbh_ch1_debug2) 51 mxs_reg_32(hw_apbh_ch2_curcmdar) 52 mxs_reg_32(hw_apbh_ch2_nxtcmdar) 53 mxs_reg_32(hw_apbh_ch2_cmd) 54 mxs_reg_32(hw_apbh_ch2_bar) 55 mxs_reg_32(hw_apbh_ch2_sema) 56 mxs_reg_32(hw_apbh_ch2_debug1) 57 mxs_reg_32(hw_apbh_ch2_debug2) 58 mxs_reg_32(hw_apbh_ch3_curcmdar) 59 mxs_reg_32(hw_apbh_ch3_nxtcmdar) 60 mxs_reg_32(hw_apbh_ch3_cmd) 61 mxs_reg_32(hw_apbh_ch3_bar) 62 mxs_reg_32(hw_apbh_ch3_sema) 63 mxs_reg_32(hw_apbh_ch3_debug1) 64 mxs_reg_32(hw_apbh_ch3_debug2) 65 mxs_reg_32(hw_apbh_ch4_curcmdar) 66 mxs_reg_32(hw_apbh_ch4_nxtcmdar) 67 mxs_reg_32(hw_apbh_ch4_cmd) 68 mxs_reg_32(hw_apbh_ch4_bar) 69 mxs_reg_32(hw_apbh_ch4_sema) 70 mxs_reg_32(hw_apbh_ch4_debug1) 71 mxs_reg_32(hw_apbh_ch4_debug2) 72 mxs_reg_32(hw_apbh_ch5_curcmdar) 73 mxs_reg_32(hw_apbh_ch5_nxtcmdar) 74 mxs_reg_32(hw_apbh_ch5_cmd) 75 mxs_reg_32(hw_apbh_ch5_bar) 76 mxs_reg_32(hw_apbh_ch5_sema) 77 mxs_reg_32(hw_apbh_ch5_debug1) 78 mxs_reg_32(hw_apbh_ch5_debug2) 79 mxs_reg_32(hw_apbh_ch6_curcmdar) 80 mxs_reg_32(hw_apbh_ch6_nxtcmdar) 81 mxs_reg_32(hw_apbh_ch6_cmd) 82 mxs_reg_32(hw_apbh_ch6_bar) 83 mxs_reg_32(hw_apbh_ch6_sema) 84 mxs_reg_32(hw_apbh_ch6_debug1) 85 mxs_reg_32(hw_apbh_ch6_debug2) 86 mxs_reg_32(hw_apbh_ch7_curcmdar) 87 mxs_reg_32(hw_apbh_ch7_nxtcmdar) 88 mxs_reg_32(hw_apbh_ch7_cmd) 89 mxs_reg_32(hw_apbh_ch7_bar) 90 mxs_reg_32(hw_apbh_ch7_sema) 91 mxs_reg_32(hw_apbh_ch7_debug1) 92 mxs_reg_32(hw_apbh_ch7_debug2) 93 }; 94 }; 95 mxs_reg_32(hw_apbh_version) 96 }; 97 98 #elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7)) 99 struct mxs_apbh_regs { 100 mxs_reg_32(hw_apbh_ctrl0) 101 mxs_reg_32(hw_apbh_ctrl1) 102 mxs_reg_32(hw_apbh_ctrl2) 103 mxs_reg_32(hw_apbh_channel_ctrl) 104 mxs_reg_32(hw_apbh_devsel) 105 mxs_reg_32(hw_apbh_dma_burst_size) 106 mxs_reg_32(hw_apbh_debug) 107 108 uint32_t reserved[36]; 109 110 union { 111 struct { 112 mxs_reg_32(hw_apbh_ch_curcmdar) 113 mxs_reg_32(hw_apbh_ch_nxtcmdar) 114 mxs_reg_32(hw_apbh_ch_cmd) 115 mxs_reg_32(hw_apbh_ch_bar) 116 mxs_reg_32(hw_apbh_ch_sema) 117 mxs_reg_32(hw_apbh_ch_debug1) 118 mxs_reg_32(hw_apbh_ch_debug2) 119 } ch[16]; 120 struct { 121 mxs_reg_32(hw_apbh_ch0_curcmdar) 122 mxs_reg_32(hw_apbh_ch0_nxtcmdar) 123 mxs_reg_32(hw_apbh_ch0_cmd) 124 mxs_reg_32(hw_apbh_ch0_bar) 125 mxs_reg_32(hw_apbh_ch0_sema) 126 mxs_reg_32(hw_apbh_ch0_debug1) 127 mxs_reg_32(hw_apbh_ch0_debug2) 128 mxs_reg_32(hw_apbh_ch1_curcmdar) 129 mxs_reg_32(hw_apbh_ch1_nxtcmdar) 130 mxs_reg_32(hw_apbh_ch1_cmd) 131 mxs_reg_32(hw_apbh_ch1_bar) 132 mxs_reg_32(hw_apbh_ch1_sema) 133 mxs_reg_32(hw_apbh_ch1_debug1) 134 mxs_reg_32(hw_apbh_ch1_debug2) 135 mxs_reg_32(hw_apbh_ch2_curcmdar) 136 mxs_reg_32(hw_apbh_ch2_nxtcmdar) 137 mxs_reg_32(hw_apbh_ch2_cmd) 138 mxs_reg_32(hw_apbh_ch2_bar) 139 mxs_reg_32(hw_apbh_ch2_sema) 140 mxs_reg_32(hw_apbh_ch2_debug1) 141 mxs_reg_32(hw_apbh_ch2_debug2) 142 mxs_reg_32(hw_apbh_ch3_curcmdar) 143 mxs_reg_32(hw_apbh_ch3_nxtcmdar) 144 mxs_reg_32(hw_apbh_ch3_cmd) 145 mxs_reg_32(hw_apbh_ch3_bar) 146 mxs_reg_32(hw_apbh_ch3_sema) 147 mxs_reg_32(hw_apbh_ch3_debug1) 148 mxs_reg_32(hw_apbh_ch3_debug2) 149 mxs_reg_32(hw_apbh_ch4_curcmdar) 150 mxs_reg_32(hw_apbh_ch4_nxtcmdar) 151 mxs_reg_32(hw_apbh_ch4_cmd) 152 mxs_reg_32(hw_apbh_ch4_bar) 153 mxs_reg_32(hw_apbh_ch4_sema) 154 mxs_reg_32(hw_apbh_ch4_debug1) 155 mxs_reg_32(hw_apbh_ch4_debug2) 156 mxs_reg_32(hw_apbh_ch5_curcmdar) 157 mxs_reg_32(hw_apbh_ch5_nxtcmdar) 158 mxs_reg_32(hw_apbh_ch5_cmd) 159 mxs_reg_32(hw_apbh_ch5_bar) 160 mxs_reg_32(hw_apbh_ch5_sema) 161 mxs_reg_32(hw_apbh_ch5_debug1) 162 mxs_reg_32(hw_apbh_ch5_debug2) 163 mxs_reg_32(hw_apbh_ch6_curcmdar) 164 mxs_reg_32(hw_apbh_ch6_nxtcmdar) 165 mxs_reg_32(hw_apbh_ch6_cmd) 166 mxs_reg_32(hw_apbh_ch6_bar) 167 mxs_reg_32(hw_apbh_ch6_sema) 168 mxs_reg_32(hw_apbh_ch6_debug1) 169 mxs_reg_32(hw_apbh_ch6_debug2) 170 mxs_reg_32(hw_apbh_ch7_curcmdar) 171 mxs_reg_32(hw_apbh_ch7_nxtcmdar) 172 mxs_reg_32(hw_apbh_ch7_cmd) 173 mxs_reg_32(hw_apbh_ch7_bar) 174 mxs_reg_32(hw_apbh_ch7_sema) 175 mxs_reg_32(hw_apbh_ch7_debug1) 176 mxs_reg_32(hw_apbh_ch7_debug2) 177 mxs_reg_32(hw_apbh_ch8_curcmdar) 178 mxs_reg_32(hw_apbh_ch8_nxtcmdar) 179 mxs_reg_32(hw_apbh_ch8_cmd) 180 mxs_reg_32(hw_apbh_ch8_bar) 181 mxs_reg_32(hw_apbh_ch8_sema) 182 mxs_reg_32(hw_apbh_ch8_debug1) 183 mxs_reg_32(hw_apbh_ch8_debug2) 184 mxs_reg_32(hw_apbh_ch9_curcmdar) 185 mxs_reg_32(hw_apbh_ch9_nxtcmdar) 186 mxs_reg_32(hw_apbh_ch9_cmd) 187 mxs_reg_32(hw_apbh_ch9_bar) 188 mxs_reg_32(hw_apbh_ch9_sema) 189 mxs_reg_32(hw_apbh_ch9_debug1) 190 mxs_reg_32(hw_apbh_ch9_debug2) 191 mxs_reg_32(hw_apbh_ch10_curcmdar) 192 mxs_reg_32(hw_apbh_ch10_nxtcmdar) 193 mxs_reg_32(hw_apbh_ch10_cmd) 194 mxs_reg_32(hw_apbh_ch10_bar) 195 mxs_reg_32(hw_apbh_ch10_sema) 196 mxs_reg_32(hw_apbh_ch10_debug1) 197 mxs_reg_32(hw_apbh_ch10_debug2) 198 mxs_reg_32(hw_apbh_ch11_curcmdar) 199 mxs_reg_32(hw_apbh_ch11_nxtcmdar) 200 mxs_reg_32(hw_apbh_ch11_cmd) 201 mxs_reg_32(hw_apbh_ch11_bar) 202 mxs_reg_32(hw_apbh_ch11_sema) 203 mxs_reg_32(hw_apbh_ch11_debug1) 204 mxs_reg_32(hw_apbh_ch11_debug2) 205 mxs_reg_32(hw_apbh_ch12_curcmdar) 206 mxs_reg_32(hw_apbh_ch12_nxtcmdar) 207 mxs_reg_32(hw_apbh_ch12_cmd) 208 mxs_reg_32(hw_apbh_ch12_bar) 209 mxs_reg_32(hw_apbh_ch12_sema) 210 mxs_reg_32(hw_apbh_ch12_debug1) 211 mxs_reg_32(hw_apbh_ch12_debug2) 212 mxs_reg_32(hw_apbh_ch13_curcmdar) 213 mxs_reg_32(hw_apbh_ch13_nxtcmdar) 214 mxs_reg_32(hw_apbh_ch13_cmd) 215 mxs_reg_32(hw_apbh_ch13_bar) 216 mxs_reg_32(hw_apbh_ch13_sema) 217 mxs_reg_32(hw_apbh_ch13_debug1) 218 mxs_reg_32(hw_apbh_ch13_debug2) 219 mxs_reg_32(hw_apbh_ch14_curcmdar) 220 mxs_reg_32(hw_apbh_ch14_nxtcmdar) 221 mxs_reg_32(hw_apbh_ch14_cmd) 222 mxs_reg_32(hw_apbh_ch14_bar) 223 mxs_reg_32(hw_apbh_ch14_sema) 224 mxs_reg_32(hw_apbh_ch14_debug1) 225 mxs_reg_32(hw_apbh_ch14_debug2) 226 mxs_reg_32(hw_apbh_ch15_curcmdar) 227 mxs_reg_32(hw_apbh_ch15_nxtcmdar) 228 mxs_reg_32(hw_apbh_ch15_cmd) 229 mxs_reg_32(hw_apbh_ch15_bar) 230 mxs_reg_32(hw_apbh_ch15_sema) 231 mxs_reg_32(hw_apbh_ch15_debug1) 232 mxs_reg_32(hw_apbh_ch15_debug2) 233 }; 234 }; 235 mxs_reg_32(hw_apbh_version) 236 }; 237 #endif 238 239 #endif 240 241 #define APBH_CTRL0_SFTRST (1 << 31) 242 #define APBH_CTRL0_CLKGATE (1 << 30) 243 #define APBH_CTRL0_AHB_BURST8_EN (1 << 29) 244 #define APBH_CTRL0_APB_BURST_EN (1 << 28) 245 #if defined(CONFIG_MX23) 246 #define APBH_CTRL0_RSVD0_MASK (0xf << 24) 247 #define APBH_CTRL0_RSVD0_OFFSET 24 248 #define APBH_CTRL0_RESET_CHANNEL_MASK (0xff << 16) 249 #define APBH_CTRL0_RESET_CHANNEL_OFFSET 16 250 #define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xff << 8) 251 #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 8 252 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x02 253 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x04 254 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x10 255 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x20 256 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x40 257 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x80 258 #elif defined(CONFIG_MX28) 259 #define APBH_CTRL0_RSVD0_MASK (0xfff << 16) 260 #define APBH_CTRL0_RSVD0_OFFSET 16 261 #define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff 262 #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 263 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x0001 264 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x0002 265 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP2 0x0004 266 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP3 0x0008 267 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0010 268 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0020 269 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0040 270 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0080 271 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0100 272 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0200 273 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0400 274 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800 275 #define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000 276 #define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000 277 #elif (defined(CONFIG_MX6) || defined(CONFIG_MX7)) 278 #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 279 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001 280 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002 281 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x0004 282 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x0008 283 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND4 0x0010 284 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND5 0x0020 285 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND6 0x0040 286 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0080 287 #define APBH_CTRL0_CLKGATE_CHANNEL_SSP 0x0100 288 #endif 289 290 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31) 291 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30) 292 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN (1 << 29) 293 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN (1 << 28) 294 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN (1 << 27) 295 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN (1 << 26) 296 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN (1 << 25) 297 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN (1 << 24) 298 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN (1 << 23) 299 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN (1 << 22) 300 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN (1 << 21) 301 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN (1 << 20) 302 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN (1 << 19) 303 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN (1 << 18) 304 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN (1 << 17) 305 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN (1 << 16) 306 #define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET 16 307 #define APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_MASK (0xffff << 16) 308 #define APBH_CTRL1_CH15_CMDCMPLT_IRQ (1 << 15) 309 #define APBH_CTRL1_CH14_CMDCMPLT_IRQ (1 << 14) 310 #define APBH_CTRL1_CH13_CMDCMPLT_IRQ (1 << 13) 311 #define APBH_CTRL1_CH12_CMDCMPLT_IRQ (1 << 12) 312 #define APBH_CTRL1_CH11_CMDCMPLT_IRQ (1 << 11) 313 #define APBH_CTRL1_CH10_CMDCMPLT_IRQ (1 << 10) 314 #define APBH_CTRL1_CH9_CMDCMPLT_IRQ (1 << 9) 315 #define APBH_CTRL1_CH8_CMDCMPLT_IRQ (1 << 8) 316 #define APBH_CTRL1_CH7_CMDCMPLT_IRQ (1 << 7) 317 #define APBH_CTRL1_CH6_CMDCMPLT_IRQ (1 << 6) 318 #define APBH_CTRL1_CH5_CMDCMPLT_IRQ (1 << 5) 319 #define APBH_CTRL1_CH4_CMDCMPLT_IRQ (1 << 4) 320 #define APBH_CTRL1_CH3_CMDCMPLT_IRQ (1 << 3) 321 #define APBH_CTRL1_CH2_CMDCMPLT_IRQ (1 << 2) 322 #define APBH_CTRL1_CH1_CMDCMPLT_IRQ (1 << 1) 323 #define APBH_CTRL1_CH0_CMDCMPLT_IRQ (1 << 0) 324 325 #define APBH_CTRL2_CH15_ERROR_STATUS (1 << 31) 326 #define APBH_CTRL2_CH14_ERROR_STATUS (1 << 30) 327 #define APBH_CTRL2_CH13_ERROR_STATUS (1 << 29) 328 #define APBH_CTRL2_CH12_ERROR_STATUS (1 << 28) 329 #define APBH_CTRL2_CH11_ERROR_STATUS (1 << 27) 330 #define APBH_CTRL2_CH10_ERROR_STATUS (1 << 26) 331 #define APBH_CTRL2_CH9_ERROR_STATUS (1 << 25) 332 #define APBH_CTRL2_CH8_ERROR_STATUS (1 << 24) 333 #define APBH_CTRL2_CH7_ERROR_STATUS (1 << 23) 334 #define APBH_CTRL2_CH6_ERROR_STATUS (1 << 22) 335 #define APBH_CTRL2_CH5_ERROR_STATUS (1 << 21) 336 #define APBH_CTRL2_CH4_ERROR_STATUS (1 << 20) 337 #define APBH_CTRL2_CH3_ERROR_STATUS (1 << 19) 338 #define APBH_CTRL2_CH2_ERROR_STATUS (1 << 18) 339 #define APBH_CTRL2_CH1_ERROR_STATUS (1 << 17) 340 #define APBH_CTRL2_CH0_ERROR_STATUS (1 << 16) 341 #define APBH_CTRL2_CH15_ERROR_IRQ (1 << 15) 342 #define APBH_CTRL2_CH14_ERROR_IRQ (1 << 14) 343 #define APBH_CTRL2_CH13_ERROR_IRQ (1 << 13) 344 #define APBH_CTRL2_CH12_ERROR_IRQ (1 << 12) 345 #define APBH_CTRL2_CH11_ERROR_IRQ (1 << 11) 346 #define APBH_CTRL2_CH10_ERROR_IRQ (1 << 10) 347 #define APBH_CTRL2_CH9_ERROR_IRQ (1 << 9) 348 #define APBH_CTRL2_CH8_ERROR_IRQ (1 << 8) 349 #define APBH_CTRL2_CH7_ERROR_IRQ (1 << 7) 350 #define APBH_CTRL2_CH6_ERROR_IRQ (1 << 6) 351 #define APBH_CTRL2_CH5_ERROR_IRQ (1 << 5) 352 #define APBH_CTRL2_CH4_ERROR_IRQ (1 << 4) 353 #define APBH_CTRL2_CH3_ERROR_IRQ (1 << 3) 354 #define APBH_CTRL2_CH2_ERROR_IRQ (1 << 2) 355 #define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1) 356 #define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0) 357 358 #if defined(CONFIG_MX28) 359 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16) 360 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 361 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16) 362 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP1 (0x0002 << 16) 363 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP2 (0x0004 << 16) 364 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP3 (0x0008 << 16) 365 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND0 (0x0010 << 16) 366 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND1 (0x0020 << 16) 367 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND2 (0x0040 << 16) 368 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND3 (0x0080 << 16) 369 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND4 (0x0100 << 16) 370 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND5 (0x0200 << 16) 371 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND6 (0x0400 << 16) 372 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_NAND7 (0x0800 << 16) 373 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_HSADC (0x1000 << 16) 374 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_LCDIF (0x2000 << 16) 375 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK 0xffff 376 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET 0 377 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP0 0x0001 378 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP1 0x0002 379 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP2 0x0004 380 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SSP3 0x0008 381 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND0 0x0010 382 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND1 0x0020 383 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND2 0x0040 384 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND3 0x0080 385 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND4 0x0100 386 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND5 0x0200 387 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND6 0x0400 388 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800 389 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000 390 #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000 391 #endif 392 393 #if (defined(CONFIG_MX6) || defined(CONFIG_MX7)) 394 #define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 395 #endif 396 397 #if defined(CONFIG_MX23) 398 #define APBH_DEVSEL_CH7_MASK (0xf << 28) 399 #define APBH_DEVSEL_CH7_OFFSET 28 400 #define APBH_DEVSEL_CH6_MASK (0xf << 24) 401 #define APBH_DEVSEL_CH6_OFFSET 24 402 #define APBH_DEVSEL_CH5_MASK (0xf << 20) 403 #define APBH_DEVSEL_CH5_OFFSET 20 404 #define APBH_DEVSEL_CH4_MASK (0xf << 16) 405 #define APBH_DEVSEL_CH4_OFFSET 16 406 #define APBH_DEVSEL_CH3_MASK (0xf << 12) 407 #define APBH_DEVSEL_CH3_OFFSET 12 408 #define APBH_DEVSEL_CH2_MASK (0xf << 8) 409 #define APBH_DEVSEL_CH2_OFFSET 8 410 #define APBH_DEVSEL_CH1_MASK (0xf << 4) 411 #define APBH_DEVSEL_CH1_OFFSET 4 412 #define APBH_DEVSEL_CH0_MASK (0xf << 0) 413 #define APBH_DEVSEL_CH0_OFFSET 0 414 #elif defined(CONFIG_MX28) 415 #define APBH_DEVSEL_CH15_MASK (0x3 << 30) 416 #define APBH_DEVSEL_CH15_OFFSET 30 417 #define APBH_DEVSEL_CH14_MASK (0x3 << 28) 418 #define APBH_DEVSEL_CH14_OFFSET 28 419 #define APBH_DEVSEL_CH13_MASK (0x3 << 26) 420 #define APBH_DEVSEL_CH13_OFFSET 26 421 #define APBH_DEVSEL_CH12_MASK (0x3 << 24) 422 #define APBH_DEVSEL_CH12_OFFSET 24 423 #define APBH_DEVSEL_CH11_MASK (0x3 << 22) 424 #define APBH_DEVSEL_CH11_OFFSET 22 425 #define APBH_DEVSEL_CH10_MASK (0x3 << 20) 426 #define APBH_DEVSEL_CH10_OFFSET 20 427 #define APBH_DEVSEL_CH9_MASK (0x3 << 18) 428 #define APBH_DEVSEL_CH9_OFFSET 18 429 #define APBH_DEVSEL_CH8_MASK (0x3 << 16) 430 #define APBH_DEVSEL_CH8_OFFSET 16 431 #define APBH_DEVSEL_CH7_MASK (0x3 << 14) 432 #define APBH_DEVSEL_CH7_OFFSET 14 433 #define APBH_DEVSEL_CH6_MASK (0x3 << 12) 434 #define APBH_DEVSEL_CH6_OFFSET 12 435 #define APBH_DEVSEL_CH5_MASK (0x3 << 10) 436 #define APBH_DEVSEL_CH5_OFFSET 10 437 #define APBH_DEVSEL_CH4_MASK (0x3 << 8) 438 #define APBH_DEVSEL_CH4_OFFSET 8 439 #define APBH_DEVSEL_CH3_MASK (0x3 << 6) 440 #define APBH_DEVSEL_CH3_OFFSET 6 441 #define APBH_DEVSEL_CH2_MASK (0x3 << 4) 442 #define APBH_DEVSEL_CH2_OFFSET 4 443 #define APBH_DEVSEL_CH1_MASK (0x3 << 2) 444 #define APBH_DEVSEL_CH1_OFFSET 2 445 #define APBH_DEVSEL_CH0_MASK (0x3 << 0) 446 #define APBH_DEVSEL_CH0_OFFSET 0 447 #endif 448 449 #if defined(CONFIG_MX28) 450 #define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30) 451 #define APBH_DMA_BURST_SIZE_CH15_OFFSET 30 452 #define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28) 453 #define APBH_DMA_BURST_SIZE_CH14_OFFSET 28 454 #define APBH_DMA_BURST_SIZE_CH13_MASK (0x3 << 26) 455 #define APBH_DMA_BURST_SIZE_CH13_OFFSET 26 456 #define APBH_DMA_BURST_SIZE_CH12_MASK (0x3 << 24) 457 #define APBH_DMA_BURST_SIZE_CH12_OFFSET 24 458 #define APBH_DMA_BURST_SIZE_CH11_MASK (0x3 << 22) 459 #define APBH_DMA_BURST_SIZE_CH11_OFFSET 22 460 #define APBH_DMA_BURST_SIZE_CH10_MASK (0x3 << 20) 461 #define APBH_DMA_BURST_SIZE_CH10_OFFSET 20 462 #define APBH_DMA_BURST_SIZE_CH9_MASK (0x3 << 18) 463 #define APBH_DMA_BURST_SIZE_CH9_OFFSET 18 464 #define APBH_DMA_BURST_SIZE_CH8_MASK (0x3 << 16) 465 #define APBH_DMA_BURST_SIZE_CH8_OFFSET 16 466 #define APBH_DMA_BURST_SIZE_CH8_BURST0 (0x0 << 16) 467 #define APBH_DMA_BURST_SIZE_CH8_BURST4 (0x1 << 16) 468 #define APBH_DMA_BURST_SIZE_CH8_BURST8 (0x2 << 16) 469 #define APBH_DMA_BURST_SIZE_CH7_MASK (0x3 << 14) 470 #define APBH_DMA_BURST_SIZE_CH7_OFFSET 14 471 #define APBH_DMA_BURST_SIZE_CH6_MASK (0x3 << 12) 472 #define APBH_DMA_BURST_SIZE_CH6_OFFSET 12 473 #define APBH_DMA_BURST_SIZE_CH5_MASK (0x3 << 10) 474 #define APBH_DMA_BURST_SIZE_CH5_OFFSET 10 475 #define APBH_DMA_BURST_SIZE_CH4_MASK (0x3 << 8) 476 #define APBH_DMA_BURST_SIZE_CH4_OFFSET 8 477 #define APBH_DMA_BURST_SIZE_CH3_MASK (0x3 << 6) 478 #define APBH_DMA_BURST_SIZE_CH3_OFFSET 6 479 #define APBH_DMA_BURST_SIZE_CH3_BURST0 (0x0 << 6) 480 #define APBH_DMA_BURST_SIZE_CH3_BURST4 (0x1 << 6) 481 #define APBH_DMA_BURST_SIZE_CH3_BURST8 (0x2 << 6) 482 483 #define APBH_DMA_BURST_SIZE_CH2_MASK (0x3 << 4) 484 #define APBH_DMA_BURST_SIZE_CH2_OFFSET 4 485 #define APBH_DMA_BURST_SIZE_CH2_BURST0 (0x0 << 4) 486 #define APBH_DMA_BURST_SIZE_CH2_BURST4 (0x1 << 4) 487 #define APBH_DMA_BURST_SIZE_CH2_BURST8 (0x2 << 4) 488 #define APBH_DMA_BURST_SIZE_CH1_MASK (0x3 << 2) 489 #define APBH_DMA_BURST_SIZE_CH1_OFFSET 2 490 #define APBH_DMA_BURST_SIZE_CH1_BURST0 (0x0 << 2) 491 #define APBH_DMA_BURST_SIZE_CH1_BURST4 (0x1 << 2) 492 #define APBH_DMA_BURST_SIZE_CH1_BURST8 (0x2 << 2) 493 494 #define APBH_DMA_BURST_SIZE_CH0_MASK 0x3 495 #define APBH_DMA_BURST_SIZE_CH0_OFFSET 0 496 #define APBH_DMA_BURST_SIZE_CH0_BURST0 0x0 497 #define APBH_DMA_BURST_SIZE_CH0_BURST4 0x1 498 #define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2 499 500 #define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0) 501 #endif 502 503 #define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff 504 #define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0 505 506 #define APBH_CHn_NXTCMDAR_CMD_ADDR_MASK 0xffffffff 507 #define APBH_CHn_NXTCMDAR_CMD_ADDR_OFFSET 0 508 509 #define APBH_CHn_CMD_XFER_COUNT_MASK (0xffff << 16) 510 #define APBH_CHn_CMD_XFER_COUNT_OFFSET 16 511 #define APBH_CHn_CMD_CMDWORDS_MASK (0xf << 12) 512 #define APBH_CHn_CMD_CMDWORDS_OFFSET 12 513 #define APBH_CHn_CMD_HALTONTERMINATE (1 << 8) 514 #define APBH_CHn_CMD_WAIT4ENDCMD (1 << 7) 515 #define APBH_CHn_CMD_SEMAPHORE (1 << 6) 516 #define APBH_CHn_CMD_NANDWAIT4READY (1 << 5) 517 #define APBH_CHn_CMD_NANDLOCK (1 << 4) 518 #define APBH_CHn_CMD_IRQONCMPLT (1 << 3) 519 #define APBH_CHn_CMD_CHAIN (1 << 2) 520 #define APBH_CHn_CMD_COMMAND_MASK 0x3 521 #define APBH_CHn_CMD_COMMAND_OFFSET 0 522 #define APBH_CHn_CMD_COMMAND_NO_DMA_XFER 0x0 523 #define APBH_CHn_CMD_COMMAND_DMA_WRITE 0x1 524 #define APBH_CHn_CMD_COMMAND_DMA_READ 0x2 525 #define APBH_CHn_CMD_COMMAND_DMA_SENSE 0x3 526 527 #define APBH_CHn_BAR_ADDRESS_MASK 0xffffffff 528 #define APBH_CHn_BAR_ADDRESS_OFFSET 0 529 530 #define APBH_CHn_SEMA_RSVD2_MASK (0xff << 24) 531 #define APBH_CHn_SEMA_RSVD2_OFFSET 24 532 #define APBH_CHn_SEMA_PHORE_MASK (0xff << 16) 533 #define APBH_CHn_SEMA_PHORE_OFFSET 16 534 #define APBH_CHn_SEMA_RSVD1_MASK (0xff << 8) 535 #define APBH_CHn_SEMA_RSVD1_OFFSET 8 536 #define APBH_CHn_SEMA_INCREMENT_SEMA_MASK (0xff << 0) 537 #define APBH_CHn_SEMA_INCREMENT_SEMA_OFFSET 0 538 539 #define APBH_CHn_DEBUG1_REQ (1 << 31) 540 #define APBH_CHn_DEBUG1_BURST (1 << 30) 541 #define APBH_CHn_DEBUG1_KICK (1 << 29) 542 #define APBH_CHn_DEBUG1_END (1 << 28) 543 #define APBH_CHn_DEBUG1_SENSE (1 << 27) 544 #define APBH_CHn_DEBUG1_READY (1 << 26) 545 #define APBH_CHn_DEBUG1_LOCK (1 << 25) 546 #define APBH_CHn_DEBUG1_NEXTCMDADDRVALID (1 << 24) 547 #define APBH_CHn_DEBUG1_RD_FIFO_EMPTY (1 << 23) 548 #define APBH_CHn_DEBUG1_RD_FIFO_FULL (1 << 22) 549 #define APBH_CHn_DEBUG1_WR_FIFO_EMPTY (1 << 21) 550 #define APBH_CHn_DEBUG1_WR_FIFO_FULL (1 << 20) 551 #define APBH_CHn_DEBUG1_RSVD1_MASK (0x7fff << 5) 552 #define APBH_CHn_DEBUG1_RSVD1_OFFSET 5 553 #define APBH_CHn_DEBUG1_STATEMACHINE_MASK 0x1f 554 #define APBH_CHn_DEBUG1_STATEMACHINE_OFFSET 0 555 #define APBH_CHn_DEBUG1_STATEMACHINE_IDLE 0x00 556 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD1 0x01 557 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD3 0x02 558 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD2 0x03 559 #define APBH_CHn_DEBUG1_STATEMACHINE_XFER_DECODE 0x04 560 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_WAIT 0x05 561 #define APBH_CHn_DEBUG1_STATEMACHINE_REQ_CMD4 0x06 562 #define APBH_CHn_DEBUG1_STATEMACHINE_PIO_REQ 0x07 563 #define APBH_CHn_DEBUG1_STATEMACHINE_READ_FLUSH 0x08 564 #define APBH_CHn_DEBUG1_STATEMACHINE_READ_WAIT 0x09 565 #define APBH_CHn_DEBUG1_STATEMACHINE_WRITE 0x0c 566 #define APBH_CHn_DEBUG1_STATEMACHINE_READ_REQ 0x0d 567 #define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_CHAIN 0x0e 568 #define APBH_CHn_DEBUG1_STATEMACHINE_XFER_COMPLETE 0x0f 569 #define APBH_CHn_DEBUG1_STATEMACHINE_TERMINATE 0x14 570 #define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_END 0x15 571 #define APBH_CHn_DEBUG1_STATEMACHINE_WRITE_WAIT 0x1c 572 #define APBH_CHn_DEBUG1_STATEMACHINE_HALT_AFTER_TERM 0x1d 573 #define APBH_CHn_DEBUG1_STATEMACHINE_CHECK_WAIT 0x1e 574 #define APBH_CHn_DEBUG1_STATEMACHINE_WAIT_READY 0x1f 575 576 #define APBH_CHn_DEBUG2_APB_BYTES_MASK (0xffff << 16) 577 #define APBH_CHn_DEBUG2_APB_BYTES_OFFSET 16 578 #define APBH_CHn_DEBUG2_AHB_BYTES_MASK 0xffff 579 #define APBH_CHn_DEBUG2_AHB_BYTES_OFFSET 0 580 581 #define APBH_VERSION_MAJOR_MASK (0xff << 24) 582 #define APBH_VERSION_MAJOR_OFFSET 24 583 #define APBH_VERSION_MINOR_MASK (0xff << 16) 584 #define APBH_VERSION_MINOR_OFFSET 16 585 #define APBH_VERSION_STEP_MASK 0xffff 586 #define APBH_VERSION_STEP_OFFSET 0 587 588 #endif /* __REGS_APBH_H__ */ 589
