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      1 /*
      2  * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
      3  *
      4  * SPDX-License-Identifier: BSD-3-Clause
      5  */
      6 #ifndef __ARM_DEF_H__
      7 #define __ARM_DEF_H__
      8 
      9 #include <arch.h>
     10 #include <common_def.h>
     11 #include <gic_common.h>
     12 #include <interrupt_props.h>
     13 #include <platform_def.h>
     14 #include <tbbr_img_def.h>
     15 #include <utils_def.h>
     16 #include <xlat_tables_defs.h>
     17 
     18 
     19 /******************************************************************************
     20  * Definitions common to all ARM standard platforms
     21  *****************************************************************************/
     22 
     23 /* Special value used to verify platform parameters from BL2 to BL31 */
     24 #define ARM_BL31_PLAT_PARAM_VAL		0x0f1e2d3c4b5a6978ULL
     25 
     26 #define ARM_SYSTEM_COUNT		1
     27 
     28 #define ARM_CACHE_WRITEBACK_SHIFT	6
     29 
     30 /*
     31  * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
     32  * power levels have a 1:1 mapping with the MPIDR affinity levels.
     33  */
     34 #define ARM_PWR_LVL0		MPIDR_AFFLVL0
     35 #define ARM_PWR_LVL1		MPIDR_AFFLVL1
     36 #define ARM_PWR_LVL2		MPIDR_AFFLVL2
     37 
     38 /*
     39  *  Macros for local power states in ARM platforms encoded by State-ID field
     40  *  within the power-state parameter.
     41  */
     42 /* Local power state for power domains in Run state. */
     43 #define ARM_LOCAL_STATE_RUN	0
     44 /* Local power state for retention. Valid only for CPU power domains */
     45 #define ARM_LOCAL_STATE_RET	1
     46 /* Local power state for OFF/power-down. Valid for CPU and cluster power
     47    domains */
     48 #define ARM_LOCAL_STATE_OFF	2
     49 
     50 /* Memory location options for TSP */
     51 #define ARM_TRUSTED_SRAM_ID		0
     52 #define ARM_TRUSTED_DRAM_ID		1
     53 #define ARM_DRAM_ID			2
     54 
     55 /* The first 4KB of Trusted SRAM are used as shared memory */
     56 #define ARM_TRUSTED_SRAM_BASE		0x04000000
     57 #define ARM_SHARED_RAM_BASE		ARM_TRUSTED_SRAM_BASE
     58 #define ARM_SHARED_RAM_SIZE		0x00001000	/* 4 KB */
     59 
     60 /* The remaining Trusted SRAM is used to load the BL images */
     61 #define ARM_BL_RAM_BASE			(ARM_SHARED_RAM_BASE +	\
     62 					 ARM_SHARED_RAM_SIZE)
     63 #define ARM_BL_RAM_SIZE			(PLAT_ARM_TRUSTED_SRAM_SIZE -	\
     64 					 ARM_SHARED_RAM_SIZE)
     65 
     66 /*
     67  * The top 16MB of DRAM1 is configured as secure access only using the TZC
     68  *   - SCP TZC DRAM: If present, DRAM reserved for SCP use
     69  *   - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
     70  */
     71 #define ARM_TZC_DRAM1_SIZE		ULL(0x01000000)
     72 
     73 #define ARM_SCP_TZC_DRAM1_BASE		(ARM_DRAM1_BASE +		\
     74 					 ARM_DRAM1_SIZE -		\
     75 					 ARM_SCP_TZC_DRAM1_SIZE)
     76 #define ARM_SCP_TZC_DRAM1_SIZE		PLAT_ARM_SCP_TZC_DRAM1_SIZE
     77 #define ARM_SCP_TZC_DRAM1_END		(ARM_SCP_TZC_DRAM1_BASE +	\
     78 					 ARM_SCP_TZC_DRAM1_SIZE - 1)
     79 
     80 /*
     81  * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime
     82  * firmware. This region is meant to be NOLOAD and will not be zero
     83  * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be
     84  * placed here.
     85  */
     86 #define ARM_EL3_TZC_DRAM1_BASE		(ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE)
     87 #define ARM_EL3_TZC_DRAM1_SIZE		ULL(0x00200000) /* 2 MB */
     88 #define ARM_EL3_TZC_DRAM1_END		(ARM_EL3_TZC_DRAM1_BASE +	\
     89 					ARM_EL3_TZC_DRAM1_SIZE - 1)
     90 
     91 #define ARM_AP_TZC_DRAM1_BASE		(ARM_DRAM1_BASE +		\
     92 					 ARM_DRAM1_SIZE -		\
     93 					 ARM_TZC_DRAM1_SIZE)
     94 #define ARM_AP_TZC_DRAM1_SIZE		(ARM_TZC_DRAM1_SIZE -		\
     95 					 (ARM_SCP_TZC_DRAM1_SIZE +	\
     96 					 ARM_EL3_TZC_DRAM1_SIZE))
     97 #define ARM_AP_TZC_DRAM1_END		(ARM_AP_TZC_DRAM1_BASE +	\
     98 					 ARM_AP_TZC_DRAM1_SIZE - 1)
     99 
    100 /* Define the Access permissions for Secure peripherals to NS_DRAM */
    101 #if ARM_CRYPTOCELL_INTEG
    102 /*
    103  * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell.
    104  * This is required by CryptoCell to authenticate BL33 which is loaded
    105  * into the Non Secure DDR.
    106  */
    107 #define ARM_TZC_NS_DRAM_S_ACCESS	TZC_REGION_S_RD
    108 #else
    109 #define ARM_TZC_NS_DRAM_S_ACCESS	TZC_REGION_S_NONE
    110 #endif
    111 
    112 #ifdef SPD_opteed
    113 /*
    114  * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to
    115  * load/authenticate the trusted os extra image. The first 512KB of
    116  * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading
    117  * for OPTEE is paged image which only include the paging part using
    118  * virtual memory but without "init" data. OPTEE will copy the "init" data
    119  * (from pager image) to the first 512KB of TZC_DRAM, and then copy the
    120  * extra image behind the "init" data.
    121  */
    122 #define ARM_OPTEE_PAGEABLE_LOAD_BASE	(ARM_AP_TZC_DRAM1_BASE + \
    123 					 ARM_AP_TZC_DRAM1_SIZE - \
    124 					 ARM_OPTEE_PAGEABLE_LOAD_SIZE)
    125 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE	0x400000
    126 #define ARM_OPTEE_PAGEABLE_LOAD_MEM	MAP_REGION_FLAT(		\
    127 					ARM_OPTEE_PAGEABLE_LOAD_BASE,	\
    128 					ARM_OPTEE_PAGEABLE_LOAD_SIZE,	\
    129 					MT_MEMORY | MT_RW | MT_SECURE)
    130 
    131 /*
    132  * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging
    133  * support is enabled).
    134  */
    135 #define ARM_MAP_OPTEE_CORE_MEM		MAP_REGION_FLAT(		\
    136 						BL32_BASE,		\
    137 						BL32_LIMIT - BL32_BASE,	\
    138 						MT_MEMORY | MT_RW | MT_SECURE)
    139 #endif /* SPD_opteed */
    140 
    141 #define ARM_NS_DRAM1_BASE		ARM_DRAM1_BASE
    142 #define ARM_NS_DRAM1_SIZE		(ARM_DRAM1_SIZE -		\
    143 					 ARM_TZC_DRAM1_SIZE)
    144 #define ARM_NS_DRAM1_END		(ARM_NS_DRAM1_BASE +		\
    145 					 ARM_NS_DRAM1_SIZE - 1)
    146 
    147 #define ARM_DRAM1_BASE			ULL(0x80000000)
    148 #define ARM_DRAM1_SIZE			ULL(0x80000000)
    149 #define ARM_DRAM1_END			(ARM_DRAM1_BASE +		\
    150 					 ARM_DRAM1_SIZE - 1)
    151 
    152 #define ARM_DRAM2_BASE			ULL(0x880000000)
    153 #define ARM_DRAM2_SIZE			PLAT_ARM_DRAM2_SIZE
    154 #define ARM_DRAM2_END			(ARM_DRAM2_BASE +		\
    155 					 ARM_DRAM2_SIZE - 1)
    156 
    157 #define ARM_IRQ_SEC_PHY_TIMER		29
    158 
    159 #define ARM_IRQ_SEC_SGI_0		8
    160 #define ARM_IRQ_SEC_SGI_1		9
    161 #define ARM_IRQ_SEC_SGI_2		10
    162 #define ARM_IRQ_SEC_SGI_3		11
    163 #define ARM_IRQ_SEC_SGI_4		12
    164 #define ARM_IRQ_SEC_SGI_5		13
    165 #define ARM_IRQ_SEC_SGI_6		14
    166 #define ARM_IRQ_SEC_SGI_7		15
    167 
    168 /*
    169  * List of secure interrupts are deprecated, but are retained only to support
    170  * legacy configurations.
    171  */
    172 #define ARM_G1S_IRQS			ARM_IRQ_SEC_PHY_TIMER,		\
    173 					ARM_IRQ_SEC_SGI_1,		\
    174 					ARM_IRQ_SEC_SGI_2,		\
    175 					ARM_IRQ_SEC_SGI_3,		\
    176 					ARM_IRQ_SEC_SGI_4,		\
    177 					ARM_IRQ_SEC_SGI_5,		\
    178 					ARM_IRQ_SEC_SGI_7
    179 
    180 #define ARM_G0_IRQS			ARM_IRQ_SEC_SGI_0,		\
    181 					ARM_IRQ_SEC_SGI_6
    182 
    183 /*
    184  * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
    185  * terminology. On a GICv2 system or mode, the lists will be merged and treated
    186  * as Group 0 interrupts.
    187  */
    188 #define ARM_G1S_IRQ_PROPS(grp) \
    189 	INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
    190 			GIC_INTR_CFG_LEVEL), \
    191 	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
    192 			GIC_INTR_CFG_EDGE), \
    193 	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
    194 			GIC_INTR_CFG_EDGE), \
    195 	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
    196 			GIC_INTR_CFG_EDGE), \
    197 	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
    198 			GIC_INTR_CFG_EDGE), \
    199 	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
    200 			GIC_INTR_CFG_EDGE), \
    201 	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
    202 			GIC_INTR_CFG_EDGE)
    203 
    204 #define ARM_G0_IRQ_PROPS(grp) \
    205 	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
    206 			GIC_INTR_CFG_EDGE), \
    207 	INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
    208 			GIC_INTR_CFG_EDGE)
    209 
    210 #define ARM_MAP_SHARED_RAM		MAP_REGION_FLAT(		\
    211 						ARM_SHARED_RAM_BASE,	\
    212 						ARM_SHARED_RAM_SIZE,	\
    213 						MT_DEVICE | MT_RW | MT_SECURE)
    214 
    215 #define ARM_MAP_NS_DRAM1		MAP_REGION_FLAT(		\
    216 						ARM_NS_DRAM1_BASE,	\
    217 						ARM_NS_DRAM1_SIZE,	\
    218 						MT_MEMORY | MT_RW | MT_NS)
    219 
    220 #define ARM_MAP_DRAM2			MAP_REGION_FLAT(		\
    221 						ARM_DRAM2_BASE,		\
    222 						ARM_DRAM2_SIZE,		\
    223 						MT_MEMORY | MT_RW | MT_NS)
    224 #ifdef SPD_tspd
    225 
    226 #define ARM_MAP_TSP_SEC_MEM		MAP_REGION_FLAT(		\
    227 						TSP_SEC_MEM_BASE,	\
    228 						TSP_SEC_MEM_SIZE,	\
    229 						MT_MEMORY | MT_RW | MT_SECURE)
    230 #endif
    231 
    232 #if ARM_BL31_IN_DRAM
    233 #define ARM_MAP_BL31_SEC_DRAM		MAP_REGION_FLAT(		\
    234 						BL31_BASE,		\
    235 						PLAT_ARM_MAX_BL31_SIZE,	\
    236 						MT_MEMORY | MT_RW | MT_SECURE)
    237 #endif
    238 
    239 #define ARM_MAP_EL3_TZC_DRAM		MAP_REGION_FLAT(			\
    240 						ARM_EL3_TZC_DRAM1_BASE,	\
    241 						ARM_EL3_TZC_DRAM1_SIZE,	\
    242 						MT_MEMORY | MT_RW | MT_SECURE)
    243 
    244 /*
    245  * The number of regions like RO(code), coherent and data required by
    246  * different BL stages which need to be mapped in the MMU.
    247  */
    248 #if USE_COHERENT_MEM
    249 #define ARM_BL_REGIONS			3
    250 #else
    251 #define ARM_BL_REGIONS			2
    252 #endif
    253 
    254 #define MAX_MMAP_REGIONS		(PLAT_ARM_MMAP_ENTRIES +	\
    255 					 ARM_BL_REGIONS)
    256 
    257 /* Memory mapped Generic timer interfaces  */
    258 #define ARM_SYS_CNTCTL_BASE		0x2a430000
    259 #define ARM_SYS_CNTREAD_BASE		0x2a800000
    260 #define ARM_SYS_TIMCTL_BASE		0x2a810000
    261 
    262 #define ARM_CONSOLE_BAUDRATE		115200
    263 
    264 /* Trusted Watchdog constants */
    265 #define ARM_SP805_TWDG_BASE		0x2a490000
    266 #define ARM_SP805_TWDG_CLK_HZ		32768
    267 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805
    268  * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */
    269 #define ARM_TWDG_TIMEOUT_SEC		128
    270 #define ARM_TWDG_LOAD_VAL		(ARM_SP805_TWDG_CLK_HZ * 	\
    271 					 ARM_TWDG_TIMEOUT_SEC)
    272 
    273 /******************************************************************************
    274  * Required platform porting definitions common to all ARM standard platforms
    275  *****************************************************************************/
    276 
    277 /*
    278  * We need to access DRAM2 from BL2 for PSCI_MEM_PROTECT for
    279  * AArch64 builds
    280  */
    281 #ifdef AARCH64
    282 #define PLAT_PHY_ADDR_SPACE_SIZE			(1ull << 36)
    283 #define PLAT_VIRT_ADDR_SPACE_SIZE			(1ull << 36)
    284 #else
    285 #define PLAT_PHY_ADDR_SPACE_SIZE			(1ull << 32)
    286 #define PLAT_VIRT_ADDR_SPACE_SIZE			(1ull << 32)
    287 #endif
    288 
    289 
    290 /*
    291  * This macro defines the deepest retention state possible. A higher state
    292  * id will represent an invalid or a power down state.
    293  */
    294 #define PLAT_MAX_RET_STATE		ARM_LOCAL_STATE_RET
    295 
    296 /*
    297  * This macro defines the deepest power down states possible. Any state ID
    298  * higher than this is invalid.
    299  */
    300 #define PLAT_MAX_OFF_STATE		ARM_LOCAL_STATE_OFF
    301 
    302 /*
    303  * Some data must be aligned on the biggest cache line size in the platform.
    304  * This is known only to the platform as it might have a combination of
    305  * integrated and external caches.
    306  */
    307 #define CACHE_WRITEBACK_GRANULE		(1 << ARM_CACHE_WRITEBACK_SHIFT)
    308 
    309 
    310 /*******************************************************************************
    311  * BL1 specific defines.
    312  * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
    313  * addresses.
    314  ******************************************************************************/
    315 #define BL1_RO_BASE			PLAT_ARM_TRUSTED_ROM_BASE
    316 #define BL1_RO_LIMIT			(PLAT_ARM_TRUSTED_ROM_BASE	\
    317 					 + PLAT_ARM_TRUSTED_ROM_SIZE)
    318 /*
    319  * Put BL1 RW at the top of the Trusted SRAM.
    320  */
    321 #define BL1_RW_BASE			(ARM_BL_RAM_BASE +		\
    322 						ARM_BL_RAM_SIZE -	\
    323 						PLAT_ARM_MAX_BL1_RW_SIZE)
    324 #define BL1_RW_LIMIT			(ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
    325 
    326 /*******************************************************************************
    327  * BL2 specific defines.
    328  ******************************************************************************/
    329 #if ARM_BL31_IN_DRAM || (defined(AARCH32) && !defined(JUNO_AARCH32_EL3_RUNTIME))
    330 /*
    331  * For AArch32 BL31 is not applicable.
    332  * For AArch64 BL31 is loaded in the DRAM.
    333  * Put BL2 just below BL1.
    334  */
    335 #define BL2_BASE			(BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
    336 #define BL2_LIMIT			BL1_RW_BASE
    337 #else
    338 /*
    339  * Put BL2 just below BL31.
    340  */
    341 #define BL2_BASE			(BL31_BASE - PLAT_ARM_MAX_BL2_SIZE)
    342 #define BL2_LIMIT			BL31_BASE
    343 #endif
    344 
    345 /*******************************************************************************
    346  * BL31 specific defines.
    347  ******************************************************************************/
    348 #if ARM_BL31_IN_DRAM
    349 /*
    350  * Put BL31 at the bottom of TZC secured DRAM
    351  */
    352 #define BL31_BASE			ARM_AP_TZC_DRAM1_BASE
    353 #define BL31_LIMIT			(ARM_AP_TZC_DRAM1_BASE +	\
    354 						PLAT_ARM_MAX_BL31_SIZE)
    355 #elif (RESET_TO_BL31)
    356 /*
    357  * Put BL31_BASE in the middle of the Trusted SRAM.
    358  */
    359 #define BL31_BASE			(ARM_TRUSTED_SRAM_BASE + \
    360 						(PLAT_ARM_TRUSTED_SRAM_SIZE >> 1))
    361 #define BL31_LIMIT			(ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
    362 #else
    363 /*
    364  * Put BL31 at the top of the Trusted SRAM.
    365  */
    366 #define BL31_BASE			(ARM_BL_RAM_BASE +		\
    367 						ARM_BL_RAM_SIZE -	\
    368 						PLAT_ARM_MAX_BL31_SIZE)
    369 #define BL31_PROGBITS_LIMIT		BL1_RW_BASE
    370 #define BL31_LIMIT			(ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
    371 #endif
    372 
    373 /*******************************************************************************
    374  * BL32 specific defines.
    375  ******************************************************************************/
    376 /*
    377  * On ARM standard platforms, the TSP can execute from Trusted SRAM,
    378  * Trusted DRAM (if available) or the DRAM region secured by the TrustZone
    379  * controller.
    380  */
    381 #if ARM_BL31_IN_DRAM
    382 # define TSP_SEC_MEM_BASE		(ARM_AP_TZC_DRAM1_BASE +	\
    383 						PLAT_ARM_MAX_BL31_SIZE)
    384 # define TSP_SEC_MEM_SIZE		(ARM_AP_TZC_DRAM1_SIZE -	\
    385 						PLAT_ARM_MAX_BL31_SIZE)
    386 # define BL32_BASE			(ARM_AP_TZC_DRAM1_BASE +	\
    387 						PLAT_ARM_MAX_BL31_SIZE)
    388 # define BL32_LIMIT			(ARM_AP_TZC_DRAM1_BASE +	\
    389 						ARM_AP_TZC_DRAM1_SIZE)
    390 #elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID
    391 # define TSP_SEC_MEM_BASE		ARM_BL_RAM_BASE
    392 # define TSP_SEC_MEM_SIZE		ARM_BL_RAM_SIZE
    393 # define TSP_PROGBITS_LIMIT		BL2_BASE
    394 # define BL32_BASE			ARM_BL_RAM_BASE
    395 # define BL32_LIMIT			BL31_BASE
    396 #elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID
    397 # define TSP_SEC_MEM_BASE		PLAT_ARM_TRUSTED_DRAM_BASE
    398 # define TSP_SEC_MEM_SIZE		PLAT_ARM_TRUSTED_DRAM_SIZE
    399 # define BL32_BASE			PLAT_ARM_TRUSTED_DRAM_BASE
    400 # define BL32_LIMIT			(PLAT_ARM_TRUSTED_DRAM_BASE	\
    401 						+ (1 << 21))
    402 #elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
    403 # define TSP_SEC_MEM_BASE		ARM_AP_TZC_DRAM1_BASE
    404 # define TSP_SEC_MEM_SIZE		ARM_AP_TZC_DRAM1_SIZE
    405 # define BL32_BASE			ARM_AP_TZC_DRAM1_BASE
    406 # define BL32_LIMIT			(ARM_AP_TZC_DRAM1_BASE +	\
    407 						ARM_AP_TZC_DRAM1_SIZE)
    408 #else
    409 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
    410 #endif
    411 
    412 /* BL32 is mandatory in AArch32 */
    413 #ifndef AARCH32
    414 #ifdef SPD_none
    415 #undef BL32_BASE
    416 #endif /* SPD_none */
    417 #endif
    418 
    419 /*******************************************************************************
    420  * FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
    421  ******************************************************************************/
    422 #define BL2U_BASE			BL2_BASE
    423 #if ARM_BL31_IN_DRAM || (defined(AARCH32) && !defined(JUNO_AARCH32_EL3_RUNTIME))
    424 /*
    425  * For AArch32 BL31 is not applicable.
    426  * For AArch64 BL31 is loaded in the DRAM.
    427  * BL2U extends up to BL1.
    428  */
    429 #define BL2U_LIMIT			BL1_RW_BASE
    430 #else
    431 /* BL2U extends up to BL31. */
    432 #define BL2U_LIMIT			BL31_BASE
    433 #endif
    434 #define NS_BL2U_BASE			ARM_NS_DRAM1_BASE
    435 #define NS_BL1U_BASE			(PLAT_ARM_NVM_BASE + 0x03EB8000)
    436 
    437 /*
    438  * ID of the secure physical generic timer interrupt used by the TSP.
    439  */
    440 #define TSP_IRQ_SEC_PHY_TIMER		ARM_IRQ_SEC_PHY_TIMER
    441 
    442 
    443 /*
    444  * One cache line needed for bakery locks on ARM platforms
    445  */
    446 #define PLAT_PERCPU_BAKERY_LOCK_SIZE		(1 * CACHE_WRITEBACK_GRANULE)
    447 
    448 
    449 #endif /* __ARM_DEF_H__ */
    450