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Searched
defs:AvailableRegs
(Results
1 - 5
of
5
) sorted by null
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
X86CallingConv.cpp
31
SmallVector<unsigned, 5>
AvailableRegs
;
36
AvailableRegs
.push_back(Reg);
40
if (
AvailableRegs
.size() < RequiredGprsUponSplit)
47
unsigned Reg = State.AllocateReg(
AvailableRegs
[I]);
X86FrameLowering.cpp
154
const TargetRegisterClass &
AvailableRegs
= *TRI->getGPRsForTailCall(*MF);
187
for (auto CS :
AvailableRegs
)
[
all
...]
/external/llvm/lib/Target/X86/
X86FrameLowering.cpp
157
const TargetRegisterClass &
AvailableRegs
= *TRI->getGPRsForTailCall(*MF);
188
for (auto CS :
AvailableRegs
)
[
all
...]
/external/llvm/lib/Target/AArch64/
AArch64A57FPLoadBalancing.cpp
507
BitVector
AvailableRegs
= RS.getRegsAvailable(TRI->getRegClass(RegClassID));
510
AvailableRegs
&= RS.getRegsAvailable(TRI->getRegClass(RegClassID));
516
AvailableRegs
.clearBitsNotInMask(J.getRegMask());
522
AvailableRegs
.reset(*AI);
526
assert(!
AvailableRegs
[*AI] &&
536
if (!
AvailableRegs
[Reg])
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
ARMFrameLowering.cpp
[
all
...]
Completed in 73 milliseconds