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    Searched defs:BIT_0 (Results 1 - 8 of 8) sorted by null

  /frameworks/av/media/libstagefright/codecs/amrnb/common/include/
bitno_tab.h 79 #define BIT_0 0
  /frameworks/av/media/libstagefright/codecs/amrwbenc/inc/
bits.h 45 #define BIT_0 ((Word16)-127)
  /external/apache-http/src/org/apache/commons/codec/binary/
BinaryCodec.java 52 private static final int BIT_0 = 1;
75 private static final int[] BITS = {BIT_0, BIT_1, BIT_2, BIT_3, BIT_4, BIT_5, BIT_6, BIT_7};
  /frameworks/av/media/libstagefright/codecs/amrwb/src/
pvamrwbdecoder_cnst.h 133 #define BIT_0 ((int16)-127)
  /external/lzma/Asm/x86/
LzmaDecOpt.asm 255 BIT_0 macro prob:req, probNext:req
726 BIT_0 x1, x2
786 BIT_0 x2, x1
822 BIT_0 x1, x2
  /device/linaro/bootloader/edk2/OptionRomPkg/UndiRuntimeDxe/
E100b.h 201 #define BIT_0 0x0001
296 #define MDI_SR_EXT_REG_CAPABLE BIT_0 // Extended register capabilities
328 #define NWAY_EX_LP_NWAY BIT_0 // link partner is NWAY
337 #define PHY_100_ER0_FDX_INDIC BIT_0 // 1 = FDX, 0 = half duplex
508 #define CFIG_503_MII BIT_0
532 #define CFIG_PROMISCUOUS_MODE BIT_0
541 #define CFIG_STRIPPING BIT_0
  /device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/
if_mskreg.h 197 #define BIT_0 (1 << 0)
314 #define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */
343 #define PCI_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */
376 #define PCI_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */
393 #define PCI_CF1_ENA_TXBMU_WR_IDLE BIT_0 /* Enable TX BMU Write IDLE for ASPM */
406 #define PEX_DC_EN_COR_ER_RP BIT_0 /* Enable Correctable Error Reporting */
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  /external/owasp/sanitizer/lib/commons-codec-1.4/
commons-codec-1.4.jar 

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