1 /* 2 * R-Car Gen3 Clock Pulse Generator 3 * 4 * Copyright (C) 2015-2016 Glider bvba 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; version 2 of the License. 9 */ 10 11 #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__ 12 #define __CLK_RENESAS_RCAR_GEN3_CPG_H__ 13 14 enum rcar_gen3_clk_types { 15 CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM, 16 CLK_TYPE_GEN3_PLL0, 17 CLK_TYPE_GEN3_PLL1, 18 CLK_TYPE_GEN3_PLL2, 19 CLK_TYPE_GEN3_PLL3, 20 CLK_TYPE_GEN3_PLL4, 21 CLK_TYPE_GEN3_SD, 22 CLK_TYPE_GEN3_RPC, 23 CLK_TYPE_GEN3_R, 24 CLK_TYPE_GEN3_PE, 25 CLK_TYPE_GEN3_Z2, 26 }; 27 28 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ 29 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset) 30 #define DEF_GEN3_RPC(_name, _id, _parent, _offset) \ 31 DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset) 32 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ 33 _div_clean) \ 34 DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \ 35 (_parent_sscg) << 16 | (_parent_clean), \ 36 .div = (_div_sscg) << 16 | (_div_clean)) 37 38 struct rcar_gen3_cpg_pll_config { 39 u8 extal_div; 40 u8 pll1_mult; 41 u8 pll1_div; 42 u8 pll3_mult; 43 u8 pll3_div; 44 }; 45 46 #define CPG_RCKCR 0x240 47 48 struct gen3_clk_priv { 49 void __iomem *base; 50 struct cpg_mssr_info *info; 51 struct clk clk_extal; 52 struct clk clk_extalr; 53 bool sscg; 54 const struct rcar_gen3_cpg_pll_config *cpg_pll_config; 55 }; 56 57 int gen3_clk_probe(struct udevice *dev); 58 int gen3_clk_remove(struct udevice *dev); 59 60 extern const struct clk_ops gen3_clk_ops; 61 62 #endif 63
