1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2011 by Vladimir Zapolskiy <vz (at) mleia.com> 4 */ 5 6 #ifndef _LPC32XX_CLK_H 7 #define _LPC32XX_CLK_H 8 9 #include <asm/types.h> 10 11 #define OSC_CLK_FREQUENCY 13000000 12 #define RTC_CLK_FREQUENCY 32768 13 14 /* Clocking and Power Control Registers */ 15 struct clk_pm_regs { 16 u32 reserved0[5]; 17 u32 boot_map; /* Boot Map Control Register */ 18 u32 p0_intr_er; /* Port 0/1 Start and Interrupt Enable */ 19 u32 usbdiv_ctrl; /* USB Clock Pre-Divide Register */ 20 /* Internal Start Signal Sources Registers */ 21 u32 start_er_int; /* Start Enable Register */ 22 u32 start_rsr_int; /* Start Raw Status Register */ 23 u32 start_sr_int; /* Start Status Register */ 24 u32 start_apr_int; /* Start Activation Polarity Register */ 25 /* Device Pin Start Signal Sources Registers */ 26 u32 start_er_pin; /* Start Enable Register */ 27 u32 start_rsr_pin; /* Start Raw Status Register */ 28 u32 start_sr_pin; /* Start Status Register */ 29 u32 start_apr_pin; /* Start Activation Polarity Register */ 30 /* Clock Control Registers */ 31 u32 hclkdiv_ctrl; /* HCLK Divider Control Register */ 32 u32 pwr_ctrl; /* Power Control Register */ 33 u32 pll397_ctrl; /* PLL397 Control Register */ 34 u32 osc_ctrl; /* Main Oscillator Control Register */ 35 u32 sysclk_ctrl; /* SYSCLK Control Register */ 36 u32 lcdclk_ctrl; /* LCD Clock Control Register */ 37 u32 hclkpll_ctrl; /* HCLK PLL Control Register */ 38 u32 reserved1; 39 u32 adclk_ctrl1; /* ADC Clock Control1 Register */ 40 u32 usb_ctrl; /* USB Control Register */ 41 u32 sdramclk_ctrl; /* SDRAM Clock Control Register */ 42 u32 ddr_lap_nom; /* DDR Calibration Nominal Value */ 43 u32 ddr_lap_count; /* DDR Calibration Measured Value */ 44 u32 ddr_cal_delay; /* DDR Calibration Delay Value */ 45 u32 ssp_ctrl; /* SSP Control Register */ 46 u32 i2s_ctrl; /* I2S Clock Control Register */ 47 u32 ms_ctrl; /* Memory Card Control Register */ 48 u32 reserved2[3]; 49 u32 macclk_ctrl; /* Ethernet MAC Clock Control Register */ 50 u32 reserved3[4]; 51 u32 test_clk; /* Test Clock Selection Register */ 52 u32 sw_int; /* Software Interrupt Register */ 53 u32 i2cclk_ctrl; /* I2C Clock Control Register */ 54 u32 keyclk_ctrl; /* Keyboard Scan Clock Control Register */ 55 u32 adclk_ctrl; /* ADC Clock Control Register */ 56 u32 pwmclk_ctrl; /* PWM Clock Control Register */ 57 u32 timclk_ctrl; /* Watchdog and Highspeed Timer Control */ 58 u32 timclk_ctrl1; /* Motor and Timer Clock Control */ 59 u32 spi_ctrl; /* SPI Control Register */ 60 u32 flashclk_ctrl; /* NAND Flash Clock Control Register */ 61 u32 reserved4; 62 u32 u3clk; /* UART 3 Clock Control Register */ 63 u32 u4clk; /* UART 4 Clock Control Register */ 64 u32 u5clk; /* UART 5 Clock Control Register */ 65 u32 u6clk; /* UART 6 Clock Control Register */ 66 u32 irdaclk; /* IrDA Clock Control Register */ 67 u32 uartclk_ctrl; /* UART Clock Control Register */ 68 u32 dmaclk_ctrl; /* DMA Clock Control Register */ 69 u32 autoclk_ctrl; /* Autoclock Control Register */ 70 }; 71 72 /* HCLK Divider Control Register bits */ 73 #define CLK_HCLK_DDRAM_MASK (0x3 << 7) 74 #define CLK_HCLK_DDRAM_HALF (0x2 << 7) 75 #define CLK_HCLK_DDRAM_NOMINAL (0x1 << 7) 76 #define CLK_HCLK_DDRAM_STOPPED (0x0 << 7) 77 #define CLK_HCLK_PERIPH_DIV_MASK (0x1F << 2) 78 #define CLK_HCLK_PERIPH_DIV(n) ((((n) - 1) & 0x1F) << 2) 79 #define CLK_HCLK_ARM_PLL_DIV_MASK (0x3 << 0) 80 #define CLK_HCLK_ARM_PLL_DIV_4 (0x2 << 0) 81 #define CLK_HCLK_ARM_PLL_DIV_2 (0x1 << 0) 82 #define CLK_HCLK_ARM_PLL_DIV_1 (0x0 << 0) 83 84 /* Power Control Register bits */ 85 #define CLK_PWR_HCLK_RUN_PERIPH (1 << 10) 86 #define CLK_PWR_EMC_SREFREQ (1 << 9) 87 #define CLK_PWR_EMC_SREFREQ_UPDATE (1 << 8) 88 #define CLK_PWR_SDRAM_SREFREQ (1 << 7) 89 #define CLK_PWR_HIGHCORE_LEVEL (1 << 5) 90 #define CLK_PWR_SYSCLKEN_LEVEL (1 << 4) 91 #define CLK_PWR_SYSCLKEN_CTRL (1 << 3) 92 #define CLK_PWR_NORMAL_RUN (1 << 2) 93 #define CLK_PWR_HIGHCORE_CTRL (1 << 1) 94 #define CLK_PWR_STOP_MODE (1 << 0) 95 96 /* SYSCLK Control Register bits */ 97 #define CLK_SYSCLK_PLL397 (1 << 1) 98 #define CLK_SYSCLK_MUX (1 << 0) 99 100 /* HCLK PLL Control Register bits */ 101 #define CLK_HCLK_PLL_OPERATING (1 << 16) 102 #define CLK_HCLK_PLL_BYPASS (1 << 15) 103 #define CLK_HCLK_PLL_DIRECT (1 << 14) 104 #define CLK_HCLK_PLL_FEEDBACK (1 << 13) 105 #define CLK_HCLK_PLL_POSTDIV_MASK (0x3 << 11) 106 #define CLK_HCLK_PLL_POSTDIV_16 (0x3 << 11) 107 #define CLK_HCLK_PLL_POSTDIV_8 (0x2 << 11) 108 #define CLK_HCLK_PLL_POSTDIV_4 (0x1 << 11) 109 #define CLK_HCLK_PLL_POSTDIV_2 (0x0 << 11) 110 #define CLK_HCLK_PLL_PREDIV_MASK (0x3 << 9) 111 #define CLK_HCLK_PLL_PREDIV_4 (0x3 << 9) 112 #define CLK_HCLK_PLL_PREDIV_3 (0x2 << 9) 113 #define CLK_HCLK_PLL_PREDIV_2 (0x1 << 9) 114 #define CLK_HCLK_PLL_PREDIV_1 (0x0 << 9) 115 #define CLK_HCLK_PLL_FEEDBACK_DIV_MASK (0xFF << 1) 116 #define CLK_HCLK_PLL_FEEDBACK_DIV(n) ((((n) - 1) & 0xFF) << 1) 117 #define CLK_HCLK_PLL_LOCKED (1 << 0) 118 119 /* Ethernet MAC Clock Control Register bits */ 120 #define CLK_MAC_RMII (0x3 << 3) 121 #define CLK_MAC_MII (0x1 << 3) 122 #define CLK_MAC_MASTER (1 << 2) 123 #define CLK_MAC_SLAVE (1 << 1) 124 #define CLK_MAC_REG (1 << 0) 125 126 /* I2C Clock Control Register bits */ 127 #define CLK_I2C2_ENABLE (1 << 1) 128 #define CLK_I2C1_ENABLE (1 << 0) 129 130 /* Timer Clock Control1 Register bits */ 131 #define CLK_TIMCLK_MOTOR (1 << 6) 132 #define CLK_TIMCLK_TIMER3 (1 << 5) 133 #define CLK_TIMCLK_TIMER2 (1 << 4) 134 #define CLK_TIMCLK_TIMER1 (1 << 3) 135 #define CLK_TIMCLK_TIMER0 (1 << 2) 136 #define CLK_TIMCLK_TIMER5 (1 << 1) 137 #define CLK_TIMCLK_TIMER4 (1 << 0) 138 139 /* Timer Clock Control Register bits */ 140 #define CLK_TIMCLK_HSTIMER (1 << 1) 141 #define CLK_TIMCLK_WATCHDOG (1 << 0) 142 143 /* UART Clock Control Register bits */ 144 #define CLK_UART(n) (1 << ((n) - 3)) 145 146 /* UARTn Clock Select Registers bits */ 147 #define CLK_UART_HCLK (1 << 16) 148 #define CLK_UART_X_DIV(n) (((n) & 0xFF) << 8) 149 #define CLK_UART_Y_DIV(n) (((n) & 0xFF) << 0) 150 151 /* DMA Clock Control Register bits */ 152 #define CLK_DMA_ENABLE (1 << 0) 153 154 /* NAND Clock Control Register bits */ 155 #define CLK_NAND_SLC (1 << 0) 156 #define CLK_NAND_MLC (1 << 1) 157 #define CLK_NAND_SLC_SELECT (1 << 2) 158 #define CLK_NAND_MLC_INT (1 << 5) 159 160 /* SSP Clock Control Register bits */ 161 #define CLK_SSP0_ENABLE_CLOCK (1 << 0) 162 163 /* SDRAMCLK register bits */ 164 #define CLK_SDRAM_DDR_SEL (1 << 1) 165 166 /* USB control register definitions */ 167 #define CLK_USBCTRL_PLL_STS (1 << 0) 168 #define CLK_USBCTRL_FDBK_PLUS1(n) (((n) & 0xFF) << 1) 169 #define CLK_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11) 170 #define CLK_USBCTRL_PLL_PWRUP (1 << 16) 171 #define CLK_USBCTRL_CLK_EN1 (1 << 17) 172 #define CLK_USBCTRL_CLK_EN2 (1 << 18) 173 #define CLK_USBCTRL_BUS_KEEPER (0x1 << 19) 174 #define CLK_USBCTRL_USBHSTND_EN (1 << 21) 175 #define CLK_USBCTRL_USBDVND_EN (1 << 22) 176 #define CLK_USBCTRL_HCLK_EN (1 << 24) 177 178 unsigned int get_sys_clk_rate(void); 179 unsigned int get_hclk_pll_rate(void); 180 unsigned int get_hclk_clk_div(void); 181 unsigned int get_hclk_clk_rate(void); 182 unsigned int get_periph_clk_div(void); 183 unsigned int get_periph_clk_rate(void); 184 unsigned int get_sdram_clk_rate(void); 185 186 #endif /* _LPC32XX_CLK_H */ 187
