Home | History | Annotate | Download | only in arch-omap3
      1 /* SPDX-License-Identifier: GPL-2.0+ */
      2 /*
      3  * am35x_def.h - TI's AM35x specific definitions.
      4  *
      5  * Based on arch/arm/include/asm/arch-omap3/cpu.h
      6  *
      7  * Author: Ajay Kumar Gupta <ajay.gupta (at) ti.com>
      8  *
      9  * Copyright (c) 2010 Texas Instruments Incorporated
     10  */
     11 
     12 #ifndef _AM35X_DEF_H_
     13 #define _AM35X_DEF_H_
     14 
     15 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
     16 #include <asm/types.h>
     17 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
     18 
     19 #ifndef __KERNEL_STRICT_NAMES
     20 #ifndef __ASSEMBLY__
     21 
     22 /* LVL_INTR_CLEAR bits */
     23 #define USBOTGSS_INT_CLR	(1 << 4)
     24 
     25 /* IP_SW_RESET bits */
     26 #define USBOTGSS_SW_RST		(1 << 0)	/* reset USBOTG */
     27 #define CPGMACSS_SW_RST		(1 << 1)	/* reset CPGMAC */
     28 
     29 /* DEVCONF2 bits */
     30 #define CONF2_PHY_GPIOMODE	(1 << 23)
     31 #define CONF2_OTGMODE		(3 << 14)
     32 #define CONF2_NO_OVERRIDE	(0 << 14)
     33 #define CONF2_FORCE_HOST	(1 << 14)
     34 #define CONF2_FORCE_DEVICE	(2 << 14)
     35 #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14)
     36 #define CONF2_SESENDEN		(1 << 13)
     37 #define CONF2_VBDTCTEN		(1 << 12)
     38 #define CONF2_REFFREQ_24MHZ	(2 << 8)
     39 #define CONF2_REFFREQ_26MHZ	(7 << 8)
     40 #define CONF2_REFFREQ_13MHZ	(6 << 8)
     41 #define CONF2_REFFREQ		(0xf << 8)
     42 #define CONF2_PHYCLKGD		(1 << 7)
     43 #define CONF2_VBUSSENSE		(1 << 6)
     44 #define CONF2_PHY_PLLON		(1 << 5)
     45 #define CONF2_RESET		(1 << 4)
     46 #define CONF2_PHYPWRDN		(1 << 3)
     47 #define CONF2_OTGPWRDN		(1 << 2)
     48 #define CONF2_DATPOL		(1 << 1)
     49 
     50 /* General register mappings of system control module */
     51 #define AM35X_SCM_GEN_BASE	0x48002270
     52 struct am35x_scm_general {
     53 	u32 res1[0xC4];		/* 0x000 - 0x30C */
     54 	u32 devconf2;		/* 0x310 */
     55 	u32 devconf3;		/* 0x314 */
     56 	u32 res2[0x2];		/* 0x318 - 0x31C */
     57 	u32 cba_priority;	/* 0x320 */
     58 	u32 lvl_intr_clr;	/* 0x324 */
     59 	u32 ip_sw_reset;	/* 0x328 */
     60 	u32 ipss_clk_ctrl;	/* 0x32C */
     61 };
     62 #define am35x_scm_general_regs ((struct am35x_scm_general *)AM35X_SCM_GEN_BASE)
     63 
     64 #define AM35XX_IPSS_USBOTGSS_BASE	0x5C040000
     65 
     66 #endif /*__ASSEMBLY__ */
     67 #endif /* __KERNEL_STRICT_NAMES */
     68 
     69 #endif /* _AM35X_DEF_H_ */
     70