1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2004, 2011 Freescale Semiconductor. 4 * (C) Copyright 2002,2003 Motorola,Inc. 5 * Xianghua Xiao <X.Xiao (at) motorola.com> 6 */ 7 8 /* 9 * mpc8560ads board configuration file 10 * 11 * Please refer to doc/README.mpc85xx for more info. 12 * 13 * Make sure you change the MAC address and other network params first, 14 * search for CONFIG_SERVERIP, etc. in this file. 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* High Level Configuration Options */ 21 #define CONFIG_CPM2 1 /* has CPM2 */ 22 23 /* 24 * default CCARBAR is at 0xff700000 25 * assume U-Boot is less than 0.5MB 26 */ 27 28 #define CONFIG_PCI_INDIRECT_BRIDGE 29 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 30 #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 31 #define CONFIG_ENV_OVERWRITE 32 #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ 33 34 /* 35 * sysclk for MPC85xx 36 * 37 * Two valid values are: 38 * 33000000 39 * 66000000 40 * 41 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 42 * is likely the desired value here, so that is now the default. 43 * The board, however, can run at 66MHz. In any event, this value 44 * must match the settings of some switches. Details can be found 45 * in the README.mpc85xxads. 46 */ 47 48 #ifndef CONFIG_SYS_CLK_FREQ 49 #define CONFIG_SYS_CLK_FREQ 33000000 50 #endif 51 52 /* 53 * These can be toggled for performance analysis, otherwise use default. 54 */ 55 #define CONFIG_L2_CACHE /* toggle L2 cache */ 56 #define CONFIG_BTB /* toggle branch predition */ 57 58 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 59 60 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 61 #define CONFIG_SYS_MEMTEST_END 0x00400000 62 63 #define CONFIG_SYS_CCSRBAR 0xe0000000 64 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 65 66 /* DDR Setup */ 67 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 68 #define CONFIG_DDR_SPD 69 #undef CONFIG_FSL_DDR_INTERACTIVE 70 71 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 72 73 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 74 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 75 76 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 77 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 78 79 /* I2C addresses of SPD EEPROMs */ 80 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ 81 82 /* These are used when DDR doesn't use SPD. */ 83 #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ 84 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ 85 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 86 #define CONFIG_SYS_DDR_TIMING_1 0x37344321 87 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ 88 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ 89 #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ 90 #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ 91 92 /* 93 * SDRAM on the Local Bus 94 */ 95 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 96 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ 97 98 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 99 #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 100 101 #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ 102 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 103 #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ 104 #undef CONFIG_SYS_FLASH_CHECKSUM 105 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 106 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 107 108 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 109 110 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 111 #define CONFIG_SYS_RAMBOOT 112 #else 113 #undef CONFIG_SYS_RAMBOOT 114 #endif 115 116 #define CONFIG_FLASH_CFI_DRIVER 117 #define CONFIG_SYS_FLASH_CFI 118 #define CONFIG_SYS_FLASH_EMPTY_INFO 119 120 #undef CONFIG_CLOCKS_IN_MHZ 121 122 /* 123 * Local Bus Definitions 124 */ 125 126 /* 127 * Base Register 2 and Option Register 2 configure SDRAM. 128 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. 129 * 130 * For BR2, need: 131 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 132 * port-size = 32-bits = BR2[19:20] = 11 133 * no parity checking = BR2[21:22] = 00 134 * SDRAM for MSEL = BR2[24:26] = 011 135 * Valid = BR[31] = 1 136 * 137 * 0 4 8 12 16 20 24 28 138 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 139 * 140 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into 141 * FIXME: the top 17 bits of BR2. 142 */ 143 144 #define CONFIG_SYS_BR2_PRELIM 0xf0001861 145 146 /* 147 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. 148 * 149 * For OR2, need: 150 * 64MB mask for AM, OR2[0:7] = 1111 1100 151 * XAM, OR2[17:18] = 11 152 * 9 columns OR2[19-21] = 010 153 * 13 rows OR2[23-25] = 100 154 * EAD set for extra time OR[31] = 1 155 * 156 * 0 4 8 12 16 20 24 28 157 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 158 */ 159 160 #define CONFIG_SYS_OR2_PRELIM 0xfc006901 161 162 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 163 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 164 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 165 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ 166 167 #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ 168 | LSDMR_RFCR5 \ 169 | LSDMR_PRETOACT3 \ 170 | LSDMR_ACTTORW3 \ 171 | LSDMR_BL8 \ 172 | LSDMR_WRC2 \ 173 | LSDMR_CL3 \ 174 | LSDMR_RFEN \ 175 ) 176 177 /* 178 * SDRAM Controller configuration sequence. 179 */ 180 #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) 181 #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 182 #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) 183 #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) 184 #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) 185 186 /* 187 * 32KB, 8-bit wide for ADS config reg 188 */ 189 #define CONFIG_SYS_BR4_PRELIM 0xf8000801 190 #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 191 #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) 192 193 #define CONFIG_SYS_INIT_RAM_LOCK 1 194 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 195 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ 196 197 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 198 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 199 200 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 201 #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 202 203 /* Serial Port */ 204 #define CONFIG_CONS_ON_SCC /* define if console on SCC */ 205 #undef CONFIG_CONS_NONE /* define if console on something else */ 206 207 #define CONFIG_SYS_BAUDRATE_TABLE \ 208 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 209 210 /* 211 * I2C 212 */ 213 #define CONFIG_SYS_I2C 214 #define CONFIG_SYS_I2C_FSL 215 #define CONFIG_SYS_FSL_I2C_SPEED 400000 216 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 217 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 218 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 219 220 /* RapidIO MMU */ 221 #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ 222 #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ 223 #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 224 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ 225 226 /* 227 * General PCI 228 * Memory space is mapped 1-1, but I/O space must start from 0. 229 */ 230 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 231 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 232 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 233 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 234 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 235 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 236 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 237 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ 238 239 #if defined(CONFIG_PCI) 240 #undef CONFIG_EEPRO100 241 #undef CONFIG_TULIP 242 243 #if !defined(CONFIG_PCI_PNP) 244 #define PCI_ENET0_IOADDR 0xe0000000 245 #define PCI_ENET0_MEMADDR 0xe0000000 246 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 247 #endif 248 249 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 250 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 251 252 #endif /* CONFIG_PCI */ 253 254 #ifdef CONFIG_TSEC_ENET 255 256 #ifndef CONFIG_MII 257 #define CONFIG_MII 1 /* MII PHY management */ 258 #endif 259 #define CONFIG_TSEC1 1 260 #define CONFIG_TSEC1_NAME "TSEC0" 261 #define CONFIG_TSEC2 1 262 #define CONFIG_TSEC2_NAME "TSEC1" 263 #define TSEC1_PHY_ADDR 0 264 #define TSEC2_PHY_ADDR 1 265 #define TSEC1_PHYIDX 0 266 #define TSEC2_PHYIDX 0 267 #define TSEC1_FLAGS TSEC_GIGABIT 268 #define TSEC2_FLAGS TSEC_GIGABIT 269 270 /* Options are: TSEC[0-1] */ 271 #define CONFIG_ETHPRIME "TSEC0" 272 273 #endif /* CONFIG_TSEC_ENET */ 274 275 #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ 276 277 #undef CONFIG_ETHER_NONE /* define if ether on something else */ 278 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 279 280 #if (CONFIG_ETHER_INDEX == 2) 281 /* 282 * - Rx-CLK is CLK13 283 * - Tx-CLK is CLK14 284 * - Select bus for bd/buffers 285 * - Full duplex 286 */ 287 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 288 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 289 #define CONFIG_SYS_CPMFCR_RAMTYPE 0 290 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) 291 #define FETH2_RST 0x01 292 #elif (CONFIG_ETHER_INDEX == 3) 293 /* need more definitions here for FE3 */ 294 #define FETH3_RST 0x80 295 #endif /* CONFIG_ETHER_INDEX */ 296 297 #ifndef CONFIG_MII 298 #define CONFIG_MII 1 /* MII PHY management */ 299 #endif 300 301 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 302 303 /* 304 * GPIO pins used for bit-banged MII communications 305 */ 306 #define MDIO_PORT 2 /* Port C */ 307 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 308 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 309 #define MDC_DECLARE MDIO_DECLARE 310 311 #define MDIO_ACTIVE (iop->pdir |= 0x00400000) 312 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) 313 #define MDIO_READ ((iop->pdat & 0x00400000) != 0) 314 315 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ 316 else iop->pdat &= ~0x00400000 317 318 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ 319 else iop->pdat &= ~0x00200000 320 321 #define MIIDELAY udelay(1) 322 323 #endif 324 325 /* 326 * Environment 327 */ 328 #ifndef CONFIG_SYS_RAMBOOT 329 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) 330 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ 331 #define CONFIG_ENV_SIZE 0x2000 332 #else 333 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 334 #define CONFIG_ENV_SIZE 0x2000 335 #endif 336 337 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 338 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 339 340 /* 341 * BOOTP options 342 */ 343 #define CONFIG_BOOTP_BOOTFILESIZE 344 345 #undef CONFIG_WATCHDOG /* watchdog disabled */ 346 347 /* 348 * Miscellaneous configurable options 349 */ 350 #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ 351 352 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 353 354 /* 355 * For booting Linux, the board info and command line data 356 * have to be in the first 64 MB of memory, since this is 357 * the maximum mapped by the Linux kernel during initialization. 358 */ 359 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 360 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 361 362 #if defined(CONFIG_CMD_KGDB) 363 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 364 #endif 365 366 /* 367 * Environment Configuration 368 */ 369 #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 370 #define CONFIG_HAS_ETH0 371 #define CONFIG_HAS_ETH1 372 #define CONFIG_HAS_ETH2 373 #define CONFIG_HAS_ETH3 374 #endif 375 376 #define CONFIG_IPADDR 192.168.1.253 377 378 #define CONFIG_HOSTNAME "unknown" 379 #define CONFIG_ROOTPATH "/nfsroot" 380 #define CONFIG_BOOTFILE "your.uImage" 381 382 #define CONFIG_SERVERIP 192.168.1.1 383 #define CONFIG_GATEWAYIP 192.168.1.1 384 #define CONFIG_NETMASK 255.255.255.0 385 386 #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ 387 388 #define CONFIG_EXTRA_ENV_SETTINGS \ 389 "netdev=eth0\0" \ 390 "consoledev=ttyCPM\0" \ 391 "ramdiskaddr=1000000\0" \ 392 "ramdiskfile=your.ramdisk.u-boot\0" \ 393 "fdtaddr=400000\0" \ 394 "fdtfile=mpc8560ads.dtb\0" 395 396 #define CONFIG_NFSBOOTCOMMAND \ 397 "setenv bootargs root=/dev/nfs rw " \ 398 "nfsroot=$serverip:$rootpath " \ 399 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 400 "console=$consoledev,$baudrate $othbootargs;" \ 401 "tftp $loadaddr $bootfile;" \ 402 "tftp $fdtaddr $fdtfile;" \ 403 "bootm $loadaddr - $fdtaddr" 404 405 #define CONFIG_RAMBOOTCOMMAND \ 406 "setenv bootargs root=/dev/ram rw " \ 407 "console=$consoledev,$baudrate $othbootargs;" \ 408 "tftp $ramdiskaddr $ramdiskfile;" \ 409 "tftp $loadaddr $bootfile;" \ 410 "tftp $fdtaddr $fdtfile;" \ 411 "bootm $loadaddr $ramdiskaddr $fdtaddr" 412 413 #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND 414 415 #endif /* __CONFIG_H */ 416
