1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2008 4 * Sergei Poselenov, Emcraft Systems, sposelenov (at) emcraft.com. 5 * 6 * Wolfgang Denk <wd (at) denx.de> 7 * Copyright 2004 Freescale Semiconductor. 8 * (C) Copyright 2002,2003 Motorola,Inc. 9 * Xianghua Xiao <X.Xiao (at) motorola.com> 10 */ 11 12 /* 13 * Socrates 14 */ 15 16 #ifndef __CONFIG_H 17 #define __CONFIG_H 18 19 /* High Level Configuration Options */ 20 #define CONFIG_SOCRATES 1 21 22 #define CONFIG_PCI_INDIRECT_BRIDGE 23 24 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ 25 26 /* 27 * Only possible on E500 Version 2 or newer cores. 28 */ 29 #define CONFIG_ENABLE_36BIT_PHYS 1 30 31 /* 32 * sysclk for MPC85xx 33 * 34 * Two valid values are: 35 * 33000000 36 * 66000000 37 * 38 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz 39 * is likely the desired value here, so that is now the default. 40 * The board, however, can run at 66MHz. In any event, this value 41 * must match the settings of some switches. Details can be found 42 * in the README.mpc85xxads. 43 */ 44 45 #ifndef CONFIG_SYS_CLK_FREQ 46 #define CONFIG_SYS_CLK_FREQ 66666666 47 #endif 48 49 /* 50 * These can be toggled for performance analysis, otherwise use default. 51 */ 52 #define CONFIG_L2_CACHE /* toggle L2 cache */ 53 #define CONFIG_BTB /* toggle branch predition */ 54 55 #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ 56 57 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 58 #define CONFIG_SYS_MEMTEST_START 0x00400000 59 #define CONFIG_SYS_MEMTEST_END 0x00C00000 60 61 #define CONFIG_SYS_CCSRBAR 0xE0000000 62 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 63 64 /* DDR Setup */ 65 #undef CONFIG_FSL_DDR_INTERACTIVE 66 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 67 #define CONFIG_DDR_SPD 68 69 #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ 70 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 71 72 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 73 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 74 #define CONFIG_VERY_BIG_RAM 75 76 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 77 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 78 79 /* I2C addresses of SPD EEPROMs */ 80 #define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ 81 82 #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ 83 84 /* Hardcoded values, to use instead of SPD */ 85 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f 86 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 87 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 88 #define CONFIG_SYS_DDR_TIMING_1 0x3935D322 89 #define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 90 #define CONFIG_SYS_DDR_MODE 0x00480432 91 #define CONFIG_SYS_DDR_INTERVAL 0x030C0100 92 #define CONFIG_SYS_DDR_CONFIG_2 0x04400000 93 #define CONFIG_SYS_DDR_CONFIG 0xC3008000 94 #define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 95 #define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */ 96 97 /* 98 * Flash on the LocalBus 99 */ 100 #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ 101 102 #define CONFIG_SYS_FLASH0 0xFE000000 103 #define CONFIG_SYS_FLASH1 0xFC000000 104 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } 105 106 #define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ 107 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ 108 109 #define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */ 110 #define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */ 111 #define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */ 112 #define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */ 113 114 #define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ 115 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ 116 117 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 118 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ 119 #undef CONFIG_SYS_FLASH_CHECKSUM 120 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 121 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 122 123 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 124 125 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ 126 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ 127 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ 128 #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ 129 130 #define CONFIG_SYS_INIT_RAM_LOCK 1 131 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ 132 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ 133 134 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 135 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 136 137 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */ 138 #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ 139 140 /* FPGA and NAND */ 141 #define CONFIG_SYS_FPGA_BASE 0xc0000000 142 #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ 143 #define CONFIG_SYS_HMI_BASE 0xc0010000 144 #define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ 145 #define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ 146 147 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) 148 #define CONFIG_SYS_MAX_NAND_DEVICE 1 149 150 /* LIME GDC */ 151 #define CONFIG_SYS_LIME_BASE 0xc8000000 152 #define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ 153 #define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ 154 #define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */ 155 156 #define CONFIG_VIDEO_MB862xx 157 #define CONFIG_VIDEO_MB862xx_ACCEL 158 #define CONFIG_VIDEO_LOGO 159 #define CONFIG_VIDEO_BMP_LOGO 160 #define VIDEO_FB_16BPP_PIXEL_SWAP 161 #define VIDEO_FB_16BPP_WORD_SWAP 162 #define CONFIG_SPLASH_SCREEN 163 #define CONFIG_VIDEO_BMP_GZIP 164 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ 165 166 /* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */ 167 #define CONFIG_SYS_MB862xx_CCF 0x10000 168 /* SDRAM parameter */ 169 #define CONFIG_SYS_MB862xx_MMR 0x4157BA63 170 171 /* Serial Port */ 172 173 #define CONFIG_SYS_NS16550_SERIAL 174 #define CONFIG_SYS_NS16550_REG_SIZE 1 175 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 176 177 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 178 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 179 180 #define CONFIG_SYS_BAUDRATE_TABLE \ 181 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 182 183 /* 184 * I2C 185 */ 186 #define CONFIG_SYS_I2C 187 #define CONFIG_SYS_I2C_FSL 188 #define CONFIG_SYS_FSL_I2C_SPEED 102124 189 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 190 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 191 #define CONFIG_SYS_FSL_I2C2_SPEED 102124 192 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 193 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 194 195 /* I2C RTC */ 196 #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ 197 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */ 198 199 /* I2C W83782G HW-Monitoring IC */ 200 #define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */ 201 202 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 203 204 /* 205 * General PCI 206 * Memory space is mapped 1-1. 207 */ 208 #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ 209 210 /* PCI is clocked by the external source at 33 MHz */ 211 #define CONFIG_PCI_CLK_FREQ 33000000 212 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 213 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 214 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 215 #define CONFIG_SYS_PCI1_IO_BASE 0xE2000000 216 #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 217 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ 218 219 #if defined(CONFIG_PCI) 220 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 221 #endif /* CONFIG_PCI */ 222 223 #define CONFIG_MII 1 /* MII PHY management */ 224 #define CONFIG_TSEC1 1 225 #define CONFIG_TSEC1_NAME "TSEC0" 226 #define CONFIG_TSEC3 1 227 #define CONFIG_TSEC3_NAME "TSEC1" 228 #undef CONFIG_MPC85XX_FEC 229 230 #define TSEC1_PHY_ADDR 0 231 #define TSEC3_PHY_ADDR 1 232 233 #define TSEC1_PHYIDX 0 234 #define TSEC3_PHYIDX 0 235 #define TSEC1_FLAGS TSEC_GIGABIT 236 #define TSEC3_FLAGS TSEC_GIGABIT 237 238 /* Options are: TSEC[0,1] */ 239 #define CONFIG_ETHPRIME "TSEC0" 240 241 #define CONFIG_HAS_ETH0 242 #define CONFIG_HAS_ETH1 243 244 /* 245 * Environment 246 */ 247 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ 248 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 249 #define CONFIG_ENV_SIZE 0x4000 250 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) 251 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 252 253 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 254 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 255 256 #define CONFIG_TIMESTAMP /* Print image info with ts */ 257 258 /* 259 * BOOTP options 260 */ 261 #define CONFIG_BOOTP_BOOTFILESIZE 262 263 #undef CONFIG_WATCHDOG /* watchdog disabled */ 264 265 /* 266 * Miscellaneous configurable options 267 */ 268 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 269 270 /* 271 * For booting Linux, the board info and command line data 272 * have to be in the first 8 MB of memory, since this is 273 * the maximum mapped by the Linux kernel during initialization. 274 */ 275 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 276 277 #if defined(CONFIG_CMD_KGDB) 278 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ 279 #endif 280 281 #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ 282 283 284 #define CONFIG_PREBOOT "echo;" \ 285 "echo Welcome on the ABB Socrates Board;" \ 286 "echo" 287 288 #define CONFIG_EXTRA_ENV_SETTINGS \ 289 "netdev=eth0\0" \ 290 "consdev=ttyS0\0" \ 291 "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ 292 "bootfile=/home/tftp/syscon3/uImage\0" \ 293 "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \ 294 "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \ 295 "uboot_addr=FFFA0000\0" \ 296 "kernel_addr=FE000000\0" \ 297 "fdt_addr=FE1E0000\0" \ 298 "ramdisk_addr=FE200000\0" \ 299 "fdt_addr_r=B00000\0" \ 300 "kernel_addr_r=200000\0" \ 301 "ramdisk_addr_r=400000\0" \ 302 "rootpath=/opt/eldk/ppc_85xxDP\0" \ 303 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 304 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 305 "nfsroot=$serverip:$rootpath\0" \ 306 "addcons=setenv bootargs $bootargs " \ 307 "console=$consdev,$baudrate\0" \ 308 "addip=setenv bootargs $bootargs " \ 309 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ 310 ":$hostname:$netdev:off panic=1\0" \ 311 "boot_nor=run ramargs addcons;" \ 312 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 313 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 314 "tftp ${fdt_addr_r} ${fdt_file}; " \ 315 "run nfsargs addip addcons;" \ 316 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 317 "update_uboot=tftp 100000 ${uboot_file};" \ 318 "protect off fffa0000 ffffffff;" \ 319 "era fffa0000 ffffffff;" \ 320 "cp.b 100000 fffa0000 ${filesize};" \ 321 "setenv filesize;saveenv\0" \ 322 "update_kernel=tftp 100000 ${bootfile};" \ 323 "era fe000000 fe1dffff;" \ 324 "cp.b 100000 fe000000 ${filesize};" \ 325 "setenv filesize;saveenv\0" \ 326 "update_fdt=tftp 100000 ${fdt_file};" \ 327 "era fe1e0000 fe1fffff;" \ 328 "cp.b 100000 fe1e0000 ${filesize};" \ 329 "setenv filesize;saveenv\0" \ 330 "update_initrd=tftp 100000 ${initrd_file};" \ 331 "era fe200000 fe9fffff;" \ 332 "cp.b 100000 fe200000 ${filesize};" \ 333 "setenv filesize;saveenv\0" \ 334 "clean_data=era fea00000 fff5ffff\0" \ 335 "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ 336 "load_usb=usb start;" \ 337 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ 338 "boot_usb=run load_usb usbargs addcons;" \ 339 "bootm ${kernel_addr_r} - ${fdt_addr};" \ 340 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 341 "" 342 #define CONFIG_BOOTCOMMAND "run boot_nor" 343 344 /* pass open firmware flat tree */ 345 346 /* USB support */ 347 #define CONFIG_USB_OHCI_NEW 1 348 #define CONFIG_PCI_OHCI 1 349 #define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */ 350 #define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2) 351 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 352 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" 353 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 354 355 #endif /* __CONFIG_H */ 356
