1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2003 4 * Wolfgang Denk, DENX Software Engineering, wd (at) denx.de. 5 */ 6 7 /* 8 * This file contains the configuration parameters for the dbau1x00 board. 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ 15 16 #ifdef CONFIG_DBAU1000 17 /* Also known as Merlot */ 18 #define CONFIG_SOC_AU1000 1 19 #else 20 #ifdef CONFIG_DBAU1100 21 #define CONFIG_SOC_AU1100 1 22 #else 23 #ifdef CONFIG_DBAU1500 24 #define CONFIG_SOC_AU1500 1 25 #else 26 #ifdef CONFIG_DBAU1550 27 /* Cabernet */ 28 #define CONFIG_SOC_AU1550 1 29 #else 30 #error "No valid board set" 31 #endif 32 #endif 33 #endif 34 #endif 35 36 /* valid baudrates */ 37 38 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 39 40 #define CONFIG_EXTRA_ENV_SETTINGS \ 41 "addmisc=setenv bootargs ${bootargs} " \ 42 "console=ttyS0,${baudrate} " \ 43 "panic=1\0" \ 44 "bootfile=/tftpboot/vmlinux.srec\0" \ 45 "load=tftp 80500000 ${u-boot}\0" \ 46 "" 47 48 #ifdef CONFIG_DBAU1550 49 /* Boot from flash by default, revert to bootp */ 50 #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm" 51 #else /* CONFIG_DBAU1550 */ 52 #define CONFIG_BOOTCOMMAND "bootp;bootm" 53 #endif /* CONFIG_DBAU1550 */ 54 55 /* 56 * BOOTP options 57 */ 58 #define CONFIG_BOOTP_BOOTFILESIZE 59 60 /* 61 * Command line configuration. 62 */ 63 64 /* 65 * Miscellaneous configurable options 66 */ 67 68 #define CONFIG_SYS_MALLOC_LEN 128*1024 69 70 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 71 72 #define CONFIG_SYS_MHZ 396 73 74 #if (CONFIG_SYS_MHZ % 12) != 0 75 #error "Invalid CPU frequency - must be multiple of 12!" 76 #endif 77 78 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) 79 80 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ 81 82 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ 83 84 #define CONFIG_SYS_MEMTEST_START 0x80100000 85 #define CONFIG_SYS_MEMTEST_END 0x80800000 86 87 /*----------------------------------------------------------------------- 88 * FLASH and environment organization 89 */ 90 #ifdef CONFIG_DBAU1550 91 92 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 93 #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */ 94 95 #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */ 96 #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */ 97 98 #else /* CONFIG_DBAU1550 */ 99 100 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 101 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ 102 103 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ 104 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ 105 106 #endif /* CONFIG_DBAU1550 */ 107 108 #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2} 109 110 #define CONFIG_SYS_FLASH_CFI 1 111 #define CONFIG_FLASH_CFI_DRIVER 1 112 113 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 114 #define CONFIG_SYS_MONITOR_LEN (192 << 10) 115 116 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 117 118 /* We boot from this flash, selected with dip switch */ 119 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2 120 121 /* timeout values are in ticks */ 122 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 123 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ 124 125 /* Address and size of Primary Environment Sector */ 126 #define CONFIG_ENV_ADDR 0xB0030000 127 #define CONFIG_ENV_SIZE 0x10000 128 129 #define CONFIG_FLASH_16BIT 130 131 #define CONFIG_NR_DRAM_BANKS 2 132 133 #ifdef CONFIG_DBAU1550 134 #define MEM_SIZE 192 135 #else 136 #define MEM_SIZE 64 137 #endif 138 139 #define CONFIG_MEMSIZE_IN_BYTES 140 141 #ifndef CONFIG_DBAU1550 142 /*---ATA PCMCIA ------------------------------------*/ 143 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ 144 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000 145 #define CONFIG_PCMCIA_SLOT_A 146 147 #define CONFIG_ATAPI 1 148 149 /* We run CF in "true ide" mode or a harddrive via pcmcia */ 150 #define CONFIG_IDE_PCMCIA 1 151 152 /* We only support one slot for now */ 153 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 154 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 155 156 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 157 158 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 159 160 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 161 162 /* Offset for data I/O */ 163 #define CONFIG_SYS_ATA_DATA_OFFSET 8 164 165 /* Offset for normal register accesses */ 166 #define CONFIG_SYS_ATA_REG_OFFSET 0 167 168 /* Offset for alternate registers */ 169 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 170 #endif /* CONFIG_DBAU1550 */ 171 172 #endif /* __CONFIG_H */ 173
