1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2016 ARM Ltd. 4 * 5 * ARM and ARM64 barrier instructions 6 * split from armv7.h to allow sharing between ARM and ARM64 7 * 8 * Original copyright in armv7.h was: 9 * (C) Copyright 2010 Texas Instruments, <www.ti.com> Aneesh V <aneesh (at) ti.com> 10 * 11 * Much of the original barrier code was contributed by: 12 * Valentine Barshak <valentine.barshak (at) cogentembedded.com> 13 */ 14 #ifndef __BARRIERS_H__ 15 #define __BARRIERS_H__ 16 17 #ifndef __ASSEMBLY__ 18 19 #ifndef CONFIG_ARM64 20 /* 21 * CP15 Barrier instructions 22 * Please note that we have separate barrier instructions in ARMv7 23 * However, we use the CP15 based instructtions because we use 24 * -march=armv5 in U-Boot 25 */ 26 #define CP15ISB asm volatile ("mcr p15, 0, %0, c7, c5, 4" : : "r" (0)) 27 #define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)) 28 #define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0)) 29 30 #endif /* !CONFIG_ARM64 */ 31 32 #if __LINUX_ARM_ARCH__ >= 7 33 #define ISB asm volatile ("isb sy" : : : "memory") 34 #define DSB asm volatile ("dsb sy" : : : "memory") 35 #define DMB asm volatile ("dmb sy" : : : "memory") 36 #elif __LINUX_ARM_ARCH__ == 6 37 #define ISB CP15ISB 38 #define DSB CP15DSB 39 #define DMB CP15DMB 40 #else 41 #define ISB asm volatile ("" : : : "memory") 42 #define DSB CP15DSB 43 #define DMB asm volatile ("" : : : "memory") 44 #endif 45 46 #define isb() ISB 47 #define dsb() DSB 48 #define dmb() DMB 49 #endif /* __ASSEMBLY__ */ 50 #endif /* __BARRIERS_H__ */ 51
