1 /* 2 * Copyright (C) 2016 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef _CMSIS_H_ 18 #define _CMSIS_H_ 19 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 #define __NVIC_PRIO_BITS 4 26 #define __FPU_PRESENT 1 27 #define __MPU_PRESENT 1 28 29 30 31 typedef enum IRQn 32 { 33 /* ------------------- Cortex Processor Exceptions Numbers ------------------ */ 34 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 35 HardFault_IRQn = -13, /*!< 3 HardFault Interrupt */ 36 MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */ 37 BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */ 38 UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */ 39 SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */ 40 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */ 41 PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */ 42 SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */ 43 44 /* ---------------------- STM32F411 Specific Interrupt Numbers ----------------- */ 45 WWDG_IRQn = 0, 46 PVD_IRQn = 1, 47 TAMP_STAMP_IRQn = 2, 48 RTC_WKUP_IRQn = 3, 49 FLASH_IRQn = 4, 50 RCC_IRQn = 5, 51 EXTI0_IRQn = 6, 52 EXTI1_IRQn = 7, 53 EXTI2_IRQn = 8, 54 EXTI3_IRQn = 9, 55 EXTI4_IRQn = 10, 56 DMA1_Stream0_IRQn = 11, 57 DMA1_Stream1_IRQn = 12, 58 DMA1_Stream2_IRQn = 13, 59 DMA1_Stream3_IRQn = 14, 60 DMA1_Stream4_IRQn = 15, 61 DMA1_Stream5_IRQn = 16, 62 DMA1_Stream6_IRQn = 17, 63 ADC_IRQn = 18, 64 CAN1_TX_IRQn = 19, 65 CAN1_RX0_IRQn = 20, 66 CAN1_RX1_IRQn = 21, 67 CAN1_SCE_IRQn = 22, 68 EXTI9_5_IRQn = 23, 69 TIM1_BRK_TIM9_IRQn = 24, 70 TIM1_UP_TIM10_IRQn = 25, 71 TIM1_TRG_COM_TIM11_IRQn = 26, 72 TIM1_CC_IRQn = 27, 73 TIM2_IRQn = 28, 74 TIM3_IRQn = 29, 75 TIM4_IRQn = 30, 76 I2C1_EV_IRQn = 31, 77 I2C1_ER_IRQn = 32, 78 I2C2_EV_IRQn = 33, 79 I2C2_ER_IRQn = 34, 80 SPI1_IRQn = 35, 81 SPI2_IRQn = 36, 82 USART1_IRQn = 37, 83 USART2_IRQn = 38, 84 USART3_IRQn = 39, 85 EXTI15_10_IRQn = 40, 86 RTC_Alarm_IRQn = 41, 87 OTG_FS_WKUP_IRQn = 42, 88 TIM8_BRK_TIM12_IRQn = 43, 89 TIM8_UP_TIM13_IRQn = 44, 90 TIM8_TRG_COM_TIM14_IRQn = 45, 91 TIM8_CC_IRQn = 46, 92 DMA1_Stream7_IRQn = 47, 93 FSMC_IRQn = 48, 94 SDIO_IRQn = 49, 95 TIM5_IRQn = 50, 96 SPI3_IRQn = 51, 97 UART4_IRQn = 52, 98 UART5_IRQn = 53, 99 TIM6_DAC_IRQn = 54, 100 TIM7_IRQn = 55, 101 DMA2_Stream0_IRQn = 56, 102 DMA2_Stream1_IRQn = 57, 103 DMA2_Stream2_IRQn = 58, 104 DMA2_Stream3_IRQn = 59, 105 DMA2_Stream4_IRQn = 60, 106 ETH_IRQn = 61, 107 ETH_WKUP_IRQn = 62, 108 CAN2_TX_IRQn = 63, 109 CAN2_RX0_IRQn = 64, 110 CAN2_RX1_IRQn = 65, 111 CAN2_SCE_IRQn = 66, 112 OTG_FS_IRQn = 67, 113 DMA2_Stream5_IRQn = 68, 114 DMA2_Stream6_IRQn = 69, 115 DMA2_Stream7_IRQn = 70, 116 USART6_IRQn = 71, 117 I2C3_EV_IRQn = 72, 118 I2C3_ER_IRQn = 73, 119 OTG_HS_EP1_OUT_IRQn = 74, 120 OTG_HS_EP1_IN_IRQn = 75, 121 OTG_HS_WKUP_IRQn = 76, 122 OTG_HS_IRQn = 77, 123 DCMI_IRQn = 78, 124 CRYP_IRQn = 79, 125 HASH_RNG_IRQn = 80, 126 FPU_IRQn = 81, 127 NUM_INTERRUPTS 128 } IRQn_Type; 129 130 #include <cpu/cmsis.h> 131 132 #ifdef __cplusplus 133 } 134 #endif 135 136 137 #endif 138 139
