1 /* 2 * Copyright (C) 2014-2015 Etnaviv Project 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Christian Gmeiner <christian.gmeiner (at) gmail.com> 25 */ 26 27 #ifndef ETNAVIV_DRMIF_H_ 28 #define ETNAVIV_DRMIF_H_ 29 30 #include <xf86drm.h> 31 #include <stdint.h> 32 33 struct etna_bo; 34 struct etna_pipe; 35 struct etna_gpu; 36 struct etna_device; 37 struct etna_cmd_stream; 38 struct etna_perfmon; 39 struct etna_perfmon_domain; 40 struct etna_perfmon_signal; 41 42 enum etna_pipe_id { 43 ETNA_PIPE_3D = 0, 44 ETNA_PIPE_2D = 1, 45 ETNA_PIPE_VG = 2, 46 ETNA_PIPE_MAX 47 }; 48 49 enum etna_param_id { 50 ETNA_GPU_MODEL = 0x1, 51 ETNA_GPU_REVISION = 0x2, 52 ETNA_GPU_FEATURES_0 = 0x3, 53 ETNA_GPU_FEATURES_1 = 0x4, 54 ETNA_GPU_FEATURES_2 = 0x5, 55 ETNA_GPU_FEATURES_3 = 0x6, 56 ETNA_GPU_FEATURES_4 = 0x7, 57 ETNA_GPU_FEATURES_5 = 0x8, 58 ETNA_GPU_FEATURES_6 = 0x9, 59 60 ETNA_GPU_STREAM_COUNT = 0x10, 61 ETNA_GPU_REGISTER_MAX = 0x11, 62 ETNA_GPU_THREAD_COUNT = 0x12, 63 ETNA_GPU_VERTEX_CACHE_SIZE = 0x13, 64 ETNA_GPU_SHADER_CORE_COUNT = 0x14, 65 ETNA_GPU_PIXEL_PIPES = 0x15, 66 ETNA_GPU_VERTEX_OUTPUT_BUFFER_SIZE = 0x16, 67 ETNA_GPU_BUFFER_SIZE = 0x17, 68 ETNA_GPU_INSTRUCTION_COUNT = 0x18, 69 ETNA_GPU_NUM_CONSTANTS = 0x19, 70 ETNA_GPU_NUM_VARYINGS = 0x1a 71 }; 72 73 /* bo flags: */ 74 #define DRM_ETNA_GEM_CACHE_CACHED 0x00010000 75 #define DRM_ETNA_GEM_CACHE_WC 0x00020000 76 #define DRM_ETNA_GEM_CACHE_UNCACHED 0x00040000 77 #define DRM_ETNA_GEM_CACHE_MASK 0x000f0000 78 /* map flags */ 79 #define DRM_ETNA_GEM_FORCE_MMU 0x00100000 80 81 /* bo access flags: (keep aligned to ETNA_PREP_x) */ 82 #define DRM_ETNA_PREP_READ 0x01 83 #define DRM_ETNA_PREP_WRITE 0x02 84 #define DRM_ETNA_PREP_NOSYNC 0x04 85 86 /* device functions: 87 */ 88 89 struct etna_device *etna_device_new(int fd); 90 struct etna_device *etna_device_new_dup(int fd); 91 struct etna_device *etna_device_ref(struct etna_device *dev); 92 void etna_device_del(struct etna_device *dev); 93 int etna_device_fd(struct etna_device *dev); 94 95 /* gpu functions: 96 */ 97 98 struct etna_gpu *etna_gpu_new(struct etna_device *dev, unsigned int core); 99 void etna_gpu_del(struct etna_gpu *gpu); 100 int etna_gpu_get_param(struct etna_gpu *gpu, enum etna_param_id param, 101 uint64_t *value); 102 103 104 /* pipe functions: 105 */ 106 107 struct etna_pipe *etna_pipe_new(struct etna_gpu *gpu, enum etna_pipe_id id); 108 void etna_pipe_del(struct etna_pipe *pipe); 109 int etna_pipe_wait(struct etna_pipe *pipe, uint32_t timestamp, uint32_t ms); 110 int etna_pipe_wait_ns(struct etna_pipe *pipe, uint32_t timestamp, uint64_t ns); 111 112 113 /* buffer-object functions: 114 */ 115 116 struct etna_bo *etna_bo_new(struct etna_device *dev, 117 uint32_t size, uint32_t flags); 118 struct etna_bo *etna_bo_from_handle(struct etna_device *dev, 119 uint32_t handle, uint32_t size); 120 struct etna_bo *etna_bo_from_name(struct etna_device *dev, uint32_t name); 121 struct etna_bo *etna_bo_from_dmabuf(struct etna_device *dev, int fd); 122 struct etna_bo *etna_bo_ref(struct etna_bo *bo); 123 void etna_bo_del(struct etna_bo *bo); 124 int etna_bo_get_name(struct etna_bo *bo, uint32_t *name); 125 uint32_t etna_bo_handle(struct etna_bo *bo); 126 int etna_bo_dmabuf(struct etna_bo *bo); 127 uint32_t etna_bo_size(struct etna_bo *bo); 128 void * etna_bo_map(struct etna_bo *bo); 129 int etna_bo_cpu_prep(struct etna_bo *bo, uint32_t op); 130 void etna_bo_cpu_fini(struct etna_bo *bo); 131 132 133 /* cmd stream functions: 134 */ 135 136 struct etna_cmd_stream { 137 uint32_t *buffer; 138 uint32_t offset; /* in 32-bit words */ 139 uint32_t size; /* in 32-bit words */ 140 }; 141 142 struct etna_cmd_stream *etna_cmd_stream_new(struct etna_pipe *pipe, uint32_t size, 143 void (*reset_notify)(struct etna_cmd_stream *stream, void *priv), 144 void *priv); 145 void etna_cmd_stream_del(struct etna_cmd_stream *stream); 146 uint32_t etna_cmd_stream_timestamp(struct etna_cmd_stream *stream); 147 void etna_cmd_stream_flush(struct etna_cmd_stream *stream); 148 void etna_cmd_stream_flush2(struct etna_cmd_stream *stream, int in_fence_fd, 149 int *out_fence_fd); 150 void etna_cmd_stream_finish(struct etna_cmd_stream *stream); 151 152 static inline uint32_t etna_cmd_stream_avail(struct etna_cmd_stream *stream) 153 { 154 static const uint32_t END_CLEARANCE = 2; /* LINK op code */ 155 156 return stream->size - stream->offset - END_CLEARANCE; 157 } 158 159 static inline void etna_cmd_stream_reserve(struct etna_cmd_stream *stream, size_t n) 160 { 161 if (etna_cmd_stream_avail(stream) < n) 162 etna_cmd_stream_flush(stream); 163 } 164 165 static inline void etna_cmd_stream_emit(struct etna_cmd_stream *stream, uint32_t data) 166 { 167 stream->buffer[stream->offset++] = data; 168 } 169 170 static inline uint32_t etna_cmd_stream_get(struct etna_cmd_stream *stream, uint32_t offset) 171 { 172 return stream->buffer[offset]; 173 } 174 175 static inline void etna_cmd_stream_set(struct etna_cmd_stream *stream, uint32_t offset, 176 uint32_t data) 177 { 178 stream->buffer[offset] = data; 179 } 180 181 static inline uint32_t etna_cmd_stream_offset(struct etna_cmd_stream *stream) 182 { 183 return stream->offset; 184 } 185 186 struct etna_reloc { 187 struct etna_bo *bo; 188 #define ETNA_RELOC_READ 0x0001 189 #define ETNA_RELOC_WRITE 0x0002 190 uint32_t flags; 191 uint32_t offset; 192 }; 193 194 void etna_cmd_stream_reloc(struct etna_cmd_stream *stream, const struct etna_reloc *r); 195 196 /* performance monitoring functions: 197 */ 198 199 struct etna_perfmon *etna_perfmon_create(struct etna_pipe *pipe); 200 void etna_perfmon_del(struct etna_perfmon *perfmon); 201 struct etna_perfmon_domain *etna_perfmon_get_dom_by_name(struct etna_perfmon *pm, const char *name); 202 struct etna_perfmon_signal *etna_perfmon_get_sig_by_name(struct etna_perfmon_domain *dom, const char *name); 203 204 struct etna_perf { 205 #define ETNA_PM_PROCESS_PRE 0x0001 206 #define ETNA_PM_PROCESS_POST 0x0002 207 uint32_t flags; 208 uint32_t sequence; 209 struct etna_perfmon_signal *signal; 210 struct etna_bo *bo; 211 uint32_t offset; 212 }; 213 214 void etna_cmd_stream_perf(struct etna_cmd_stream *stream, const struct etna_perf *p); 215 216 #endif /* ETNAVIV_DRMIF_H_ */ 217
