1 /** @file 2 3 Provides some data structure definitions used by the SD/MMC host controller driver. 4 5 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR> 6 Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR> 7 8 This program and the accompanying materials 9 are licensed and made available under the terms and conditions of the BSD License 10 which accompanies this distribution. The full text of the license may be found at 11 http://opensource.org/licenses/bsd-license.php 12 13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 15 16 **/ 17 18 #ifndef _DW_MMC_HCI_H_ 19 #define _DW_MMC_HCI_H_ 20 21 #include <Library/CacheMaintenanceLib.h> 22 #include <Library/TimerLib.h> 23 24 #include <Protocol/PlatformDwMmc.h> 25 26 // 27 // SD Host Controller SlotInfo Register Offset 28 // 29 #define DW_MMC_HC_SLOT_OFFSET 0x40 30 31 #define DW_MMC_HC_MAX_SLOT 6 32 33 // 34 // SD Host Controller MMIO Register Offset 35 // 36 #define DW_MMC_CTRL 0x000 37 #define DW_MMC_PWREN 0x004 38 #define DW_MMC_CLKDIV 0x008 39 #define DW_MMC_CLKSRC 0x00c 40 #define DW_MMC_CLKENA 0x010 41 #define DW_MMC_TMOUT 0x014 42 #define DW_MMC_CTYPE 0x018 43 #define DW_MMC_BLKSIZ 0x01c 44 #define DW_MMC_BYTCNT 0x020 45 #define DW_MMC_INTMASK 0x024 46 #define DW_MMC_CMDARG 0x028 47 #define DW_MMC_CMD 0x02c 48 #define DW_MMC_RESP0 0x030 49 #define DW_MMC_RESP1 0x034 50 #define DW_MMC_RESP2 0x038 51 #define DW_MMC_RESP3 0x03c 52 #define DW_MMC_RINTSTS 0x044 53 #define DW_MMC_STATUS 0x048 54 #define DW_MMC_FIFOTH 0x04c 55 #define DW_MMC_GPIO 0x058 56 #define DW_MMC_DEBNCE 0x064 57 #define DW_MMC_USRID 0x068 58 #define DW_MMC_VERID 0x06c 59 #define DW_MMC_HCON 0x070 60 #define DW_MMC_UHSREG 0x074 61 #define DW_MMC_BMOD 0x080 62 #define DW_MMC_DBADDR 0x088 63 #define DW_MMC_IDSTS 0x08c 64 #define DW_MMC_IDINTEN 0x090 65 #define DW_MMC_DSCADDR 0x094 66 #define DW_MMC_BUFADDR 0x098 67 #define DW_MMC_CARDTHRCTL 0x100 68 #define DW_MMC_UHSREG_EXT 0x108 69 #define DW_MMC_ENABLE_SHIFT 0x110 70 #define DW_MMC_FIFO_START 0x200 71 72 #define GET_IDSTS_DMAC_FSM(x) (((x) >> 13) & 0xf) 73 #define IDSTS_FSM_DMA_IDLE 0 74 #define IDSTS_FSM_DMA_SUSPEND 1 75 #define IDSTS_FSM_DESC_RD 2 76 #define IDSTS_FSM_DESC_CHK 3 77 #define IDSTS_FSM_DMA_RD_REQ_WAIT 4 78 #define IDSTS_FSM_DMA_WR_REQ_WAIT 5 79 #define IDSTS_FSM_DMA_RD 6 80 #define IDSTS_FSM_DMA_WR 7 81 #define IDSTS_FSM_DESC_CLOSE 8 82 #define IDSTS_FSM_MASK 0xf 83 84 #define CMD_UPDATE_CLK 0x80202000 85 #define CMD_START_BIT (1 << 31) 86 87 #define MMC_8BIT_MODE (1 << 16) 88 #define MMC_4BIT_MODE (1 << 0) 89 #define MMC_1BIT_MODE 0 90 91 #define DW_MMC_BLOCK_SIZE 512 92 93 #define CMD_INDEX_MASK 0x3F 94 #define BIT_CMD_RESPONSE_EXPECT (1 << 6) 95 #define BIT_CMD_LONG_RESPONSE (1 << 7) 96 #define BIT_CMD_CHECK_RESPONSE_CRC (1 << 8) 97 #define BIT_CMD_DATA_EXPECTED (1 << 9) 98 #define BIT_CMD_READ (0 << 10) 99 #define BIT_CMD_WRITE (1 << 10) 100 #define BIT_CMD_BLOCK_TRANSFER (0 << 11) 101 #define BIT_CMD_STREAM_TRANSFER (1 << 11) 102 #define BIT_CMD_SEND_AUTO_STOP (1 << 12) 103 #define BIT_CMD_WAIT_PRVDATA_COMPLETE (1 << 13) 104 #define BIT_CMD_STOP_ABORT_CMD (1 << 14) 105 #define BIT_CMD_SEND_INIT (1 << 15) 106 #define BIT_CMD_UPDATE_CLOCK_ONLY (1 << 21) 107 #define BIT_CMD_READ_CEATA_DEVICE (1 << 22) 108 #define BIT_CMD_CCS_EXPECTED (1 << 23) 109 #define BIT_CMD_ENABLE_BOOT (1 << 24) 110 #define BIT_CMD_EXPECT_BOOT_ACK (1 << 25) 111 #define BIT_CMD_DISABLE_BOOT (1 << 26) 112 #define BIT_CMD_MANDATORY_BOOT (0 << 27) 113 #define BIT_CMD_ALTERNATE_BOOT (1 << 27) 114 #define BIT_CMD_VOLT_SWITCH (1 << 28) 115 #define BIT_CMD_USE_HOLD_REG (1 << 29) 116 #define BIT_CMD_START (1 << 31) 117 118 #define CMD_INDEX(x) ((x) & CMD_INDEX_MASK) 119 120 #define DW_MMC_INT_EBE (1 << 15) /* End-bit Err */ 121 #define DW_MMC_INT_SBE (1 << 13) /* Start-bit Err */ 122 #define DW_MMC_INT_HLE (1 << 12) /* Hardware-lock Err */ 123 #define DW_MMC_INT_FRUN (1 << 11) /* FIFO UN/OV RUN */ 124 #define DW_MMC_INT_DRT (1 << 9) /* Data timeout */ 125 #define DW_MMC_INT_RTO (1 << 8) /* Response timeout */ 126 #define DW_MMC_INT_DCRC (1 << 7) /* Data CRC err */ 127 #define DW_MMC_INT_RCRC (1 << 6) /* Response CRC err */ 128 #define DW_MMC_INT_RXDR (1 << 5) /* Receive FIFO data request */ 129 #define DW_MMC_INT_TXDR (1 << 4) /* Transmit FIFO data request */ 130 #define DW_MMC_INT_DTO (1 << 3) /* Data trans over */ 131 #define DW_MMC_INT_CMD_DONE (1 << 2) /* Command done */ 132 #define DW_MMC_INT_RE (1 << 1) /* Response error */ 133 134 #define DW_MMC_IDMAC_DES0_DIC (1 << 1) 135 #define DW_MMC_IDMAC_DES0_LD (1 << 2) 136 #define DW_MMC_IDMAC_DES0_FS (1 << 3) 137 #define DW_MMC_IDMAC_DES0_CH (1 << 4) 138 #define DW_MMC_IDMAC_DES0_ER (1 << 5) 139 #define DW_MMC_IDMAC_DES0_CES (1 << 30) 140 #define DW_MMC_IDMAC_DES0_OWN (1 << 31) 141 #define DW_MMC_IDMAC_DES1_BS1(x) ((x) & 0x1fff) 142 #define DW_MMC_IDMAC_DES2_BS2(x) (((x) & 0x1fff) << 13) 143 #define DW_MMC_IDMAC_SWRESET (1 << 0) 144 #define DW_MMC_IDMAC_FB (1 << 1) 145 #define DW_MMC_IDMAC_ENABLE (1 << 7) 146 147 #define DW_MMC_CTRL_RESET (1 << 0) 148 #define DW_MMC_CTRL_FIFO_RESET (1 << 1) 149 #define DW_MMC_CTRL_DMA_RESET (1 << 2) 150 #define DW_MMC_CTRL_INT_EN (1 << 4) 151 #define DW_MMC_CTRL_DMA_EN (1 << 5) 152 #define DW_MMC_CTRL_IDMAC_EN (1 << 25) 153 #define DW_MMC_CTRL_RESET_ALL (DW_MMC_CTRL_RESET | DW_MMC_CTRL_FIFO_RESET | DW_MMC_CTRL_DMA_RESET) 154 155 #define DW_MMC_STS_DATA_BUSY (1 << 9) 156 #define DW_MMC_STS_FIFO_COUNT(x) (((x) & 0x1fff) << 17) /* Number of filled locations in FIFO */ 157 #define GET_STS_FIFO_COUNT(x) (((x) >> 17) & 0x1fff) 158 159 #define DW_MMC_BMOD_SWR (1 << 0) /* Software Reset */ 160 #define DW_MMC_BMOD_FB (1 << 1) /* Fix Burst */ 161 #define DW_MMC_BMOD_DE (1 << 7) /* IDMAC Enable */ 162 163 #define DW_MMC_IDSTS_TI (1 << 0) /* Transmit Interrupt */ 164 #define DW_MMC_IDSTS_RI (1 << 1) /* Receive Interrupt */ 165 166 #define DW_MMC_FIFO_TWMARK(x) ((x) & 0xfff) 167 #define DW_MMC_FIFO_RWMARK(x) (((x) & 0x1ff) << 16) 168 #define DW_MMC_DMA_BURST_SIZE(x) (((x) & 0x7) << 28) 169 170 #define DW_MMC_CARD_RD_THR(x) (((x) & 0xfff) << 16) 171 #define DW_MMC_CARD_RD_THR_EN (1 << 0) 172 173 #define UHS_DDR_MODE (1 << 16) 174 175 #define GENCLK_DIV 7 176 177 #define DW_MMC_GPIO_CLK_DIV(x) (((x) & 0xf) << 8) 178 #define DW_MMC_GPIO_USE_SAMPLE_DLY(x) (((x) & 1) << 13) 179 #define DW_MMC_GPIO_CLK_ENABLE BIT16 180 181 #define UHSEXT_SAMPLE_PHASE(x) (((x) & 0x1f) << 16) 182 #define UHSEXT_SAMPLE_DRVPHASE(x) (((x) & 0x1f) << 21) 183 #define UHSEXT_SAMPLE_DLY(x) (((x) & 0x1f) << 26) 184 185 #define DWMMC_DMA_BUF_SIZE (512 * 8) 186 #define DWMMC_FIFO_THRESHOLD 16 187 188 #define DWMMC_INIT_CLOCK_FREQ 400 // KHz 189 190 // 191 // The transfer modes supported by SD Host Controller 192 // Simplified Spec 3.0 Table 1-2 193 // 194 typedef enum { 195 SdMmcNoData, 196 SdMmcPioMode, 197 SdMmcSdmaMode, 198 SdMmcAdmaMode 199 } DW_MMC_HC_TRANSFER_MODE; 200 201 // 202 // The maximum data length of each descriptor line 203 // 204 #define ADMA_MAX_DATA_PER_LINE 0x10000 205 206 #if 0 207 typedef struct { 208 UINT32 Valid:1; 209 UINT32 End:1; 210 UINT32 Int:1; 211 UINT32 Reserved:1; 212 UINT32 Act:2; 213 UINT32 Reserved1:10; 214 UINT32 Length:16; 215 UINT32 Address; 216 } DW_MMC_HC_ADMA_DESC_LINE; 217 #endif 218 219 220 typedef struct { 221 UINT32 Des0; 222 UINT32 Des1; 223 UINT32 Des2; 224 UINT32 Des3; 225 } DW_MMC_HC_DMA_DESC_LINE; 226 227 #define SD_MMC_SDMA_BOUNDARY 512 * 1024 228 #define SD_MMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1)) 229 230 typedef struct { 231 UINT8 FirstBar:3; // bit 0:2 232 UINT8 Reserved:1; // bit 3 233 UINT8 SlotNum:3; // bit 4:6 234 UINT8 Reserved1:1; // bit 7 235 } DW_MMC_HC_SLOT_INFO; 236 237 #if 0 238 typedef struct { 239 UINT32 TimeoutFreq:6; // bit 0:5 240 UINT32 Reserved:1; // bit 6 241 UINT32 TimeoutUnit:1; // bit 7 242 UINT32 BaseClkFreq:8; // bit 8:15 243 UINT32 MaxBlkLen:2; // bit 16:17 244 UINT32 BusWidth8:1; // bit 18 245 UINT32 Adma2:1; // bit 19 246 UINT32 Reserved2:1; // bit 20 247 UINT32 HighSpeed:1; // bit 21 248 UINT32 Sdma:1; // bit 22 249 UINT32 SuspRes:1; // bit 23 250 UINT32 Voltage33:1; // bit 24 251 UINT32 Voltage30:1; // bit 25 252 UINT32 Voltage18:1; // bit 26 253 UINT32 Reserved3:1; // bit 27 254 UINT32 SysBus64:1; // bit 28 255 UINT32 AsyncInt:1; // bit 29 256 UINT32 SlotType:2; // bit 30:31 257 UINT32 Sdr50:1; // bit 32 258 UINT32 Sdr104:1; // bit 33 259 UINT32 Ddr50:1; // bit 34 260 UINT32 Reserved4:1; // bit 35 261 UINT32 DriverTypeA:1; // bit 36 262 UINT32 DriverTypeC:1; // bit 37 263 UINT32 DriverTypeD:1; // bit 38 264 UINT32 DriverType4:1; // bit 39 265 UINT32 TimerCount:4; // bit 40:43 266 UINT32 Reserved5:1; // bit 44 267 UINT32 TuningSDR50:1; // bit 45 268 UINT32 RetuningMod:2; // bit 46:47 269 UINT32 ClkMultiplier:8; // bit 48:55 270 UINT32 Reserved6:7; // bit 56:62 271 UINT32 Hs400:1; // bit 63 272 } DW_MMC_HC_SLOT_CAP; 273 #endif 274 275 /** 276 Dump the content of SD/MMC host controller's Capability Register. 277 278 @param[in] Slot The slot number of the SD card to send the command to. 279 @param[in] Capability The buffer to store the capability data. 280 281 **/ 282 VOID 283 DumpCapabilityReg ( 284 IN UINT8 Slot, 285 IN DW_MMC_HC_SLOT_CAP *Capability 286 ); 287 288 /** 289 Read SlotInfo register from SD/MMC host controller pci config space. 290 291 @param[in] PciIo The PCI IO protocol instance. 292 @param[out] FirstBar The buffer to store the first BAR value. 293 @param[out] SlotNum The buffer to store the supported slot number. 294 295 @retval EFI_SUCCESS The operation succeeds. 296 @retval Others The operation fails. 297 298 **/ 299 EFI_STATUS 300 EFIAPI 301 DwMmcHcGetSlotInfo ( 302 IN EFI_PCI_IO_PROTOCOL *PciIo, 303 OUT UINT8 *FirstBar, 304 OUT UINT8 *SlotNum 305 ); 306 307 /** 308 Read/Write specified SD/MMC host controller mmio register. 309 310 @param[in] PciIo The PCI IO protocol instance. 311 @param[in] BarIndex The BAR index of the standard PCI Configuration 312 header to use as the base address for the memory 313 operation to perform. 314 @param[in] Offset The offset within the selected BAR to start the 315 memory operation. 316 @param[in] Read A boolean to indicate it's read or write operation. 317 @param[in] Count The width of the mmio register in bytes. 318 Must be 1, 2 , 4 or 8 bytes. 319 @param[in, out] Data For read operations, the destination buffer to store 320 the results. For write operations, the source buffer 321 to write data from. The caller is responsible for 322 having ownership of the data buffer and ensuring its 323 size not less than Count bytes. 324 325 @retval EFI_INVALID_PARAMETER The PciIo or Data is NULL or the Count is not valid. 326 @retval EFI_SUCCESS The read/write operation succeeds. 327 @retval Others The read/write operation fails. 328 329 **/ 330 EFI_STATUS 331 EFIAPI 332 DwMmcHcRwMmio ( 333 IN EFI_PCI_IO_PROTOCOL *PciIo, 334 IN UINT8 BarIndex, 335 IN UINT32 Offset, 336 IN BOOLEAN Read, 337 IN UINT8 Count, 338 IN OUT VOID *Data 339 ); 340 341 /** 342 Do OR operation with the value of the specified SD/MMC host controller mmio register. 343 344 @param[in] PciIo The PCI IO protocol instance. 345 @param[in] BarIndex The BAR index of the standard PCI Configuration 346 header to use as the base address for the memory 347 operation to perform. 348 @param[in] Offset The offset within the selected BAR to start the 349 memory operation. 350 @param[in] Count The width of the mmio register in bytes. 351 Must be 1, 2 , 4 or 8 bytes. 352 @param[in] OrData The pointer to the data used to do OR operation. 353 The caller is responsible for having ownership of 354 the data buffer and ensuring its size not less than 355 Count bytes. 356 357 @retval EFI_INVALID_PARAMETER The PciIo or OrData is NULL or the Count is not valid. 358 @retval EFI_SUCCESS The OR operation succeeds. 359 @retval Others The OR operation fails. 360 361 **/ 362 EFI_STATUS 363 EFIAPI 364 DwMmcHcOrMmio ( 365 IN EFI_PCI_IO_PROTOCOL *PciIo, 366 IN UINT8 BarIndex, 367 IN UINT32 Offset, 368 IN UINT8 Count, 369 IN VOID *OrData 370 ); 371 372 /** 373 Do AND operation with the value of the specified SD/MMC host controller mmio register. 374 375 @param[in] PciIo The PCI IO protocol instance. 376 @param[in] BarIndex The BAR index of the standard PCI Configuration 377 header to use as the base address for the memory 378 operation to perform. 379 @param[in] Offset The offset within the selected BAR to start the 380 memory operation. 381 @param[in] Count The width of the mmio register in bytes. 382 Must be 1, 2 , 4 or 8 bytes. 383 @param[in] AndData The pointer to the data used to do AND operation. 384 The caller is responsible for having ownership of 385 the data buffer and ensuring its size not less than 386 Count bytes. 387 388 @retval EFI_INVALID_PARAMETER The PciIo or AndData is NULL or the Count is not valid. 389 @retval EFI_SUCCESS The AND operation succeeds. 390 @retval Others The AND operation fails. 391 392 **/ 393 EFI_STATUS 394 EFIAPI 395 DwMmcHcAndMmio ( 396 IN EFI_PCI_IO_PROTOCOL *PciIo, 397 IN UINT8 BarIndex, 398 IN UINT32 Offset, 399 IN UINT8 Count, 400 IN VOID *AndData 401 ); 402 403 /** 404 Wait for the value of the specified MMIO register set to the test value. 405 406 @param[in] PciIo The PCI IO protocol instance. 407 @param[in] BarIndex The BAR index of the standard PCI Configuration 408 header to use as the base address for the memory 409 operation to perform. 410 @param[in] Offset The offset within the selected BAR to start the 411 memory operation. 412 @param[in] Count The width of the mmio register in bytes. 413 Must be 1, 2, 4 or 8 bytes. 414 @param[in] MaskValue The mask value of memory. 415 @param[in] TestValue The test value of memory. 416 @param[in] Timeout The time out value for wait memory set, uses 1 417 microsecond as a unit. 418 419 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout 420 range. 421 @retval EFI_SUCCESS The MMIO register has expected value. 422 @retval Others The MMIO operation fails. 423 424 **/ 425 EFI_STATUS 426 EFIAPI 427 DwMmcHcWaitMmioSet ( 428 IN EFI_PCI_IO_PROTOCOL *PciIo, 429 IN UINT8 BarIndex, 430 IN UINT32 Offset, 431 IN UINT8 Count, 432 IN UINT64 MaskValue, 433 IN UINT64 TestValue, 434 IN UINT64 Timeout 435 ); 436 437 /** 438 Software reset the specified SD/MMC host controller. 439 440 @param[in] PciIo The PCI IO protocol instance. 441 @param[in] Slot The slot number of the SD card to send the command to. 442 443 @retval EFI_SUCCESS The software reset executes successfully. 444 @retval Others The software reset fails. 445 446 **/ 447 EFI_STATUS 448 DwMmcHcReset ( 449 IN EFI_PCI_IO_PROTOCOL *PciIo, 450 IN UINT8 Slot, 451 IN DW_MMC_HC_SLOT_CAP Capability 452 ); 453 454 /** 455 Set all interrupt status bits in Normal and Error Interrupt Status Enable 456 register. 457 458 @param[in] PciIo The PCI IO protocol instance. 459 @param[in] Slot The slot number of the SD card to send the command to. 460 461 @retval EFI_SUCCESS The operation executes successfully. 462 @retval Others The operation fails. 463 464 **/ 465 EFI_STATUS 466 DwMmcHcEnableInterrupt ( 467 IN EFI_PCI_IO_PROTOCOL *PciIo, 468 IN UINT8 Slot 469 ); 470 471 /** 472 Get the capability data from the specified slot. 473 474 @param[in] PciIo The PCI IO protocol instance. 475 @param[in] Slot The slot number of the SD card to send the command to. 476 @param[out] Capability The buffer to store the capability data. 477 478 @retval EFI_SUCCESS The operation executes successfully. 479 @retval Others The operation fails. 480 481 **/ 482 EFI_STATUS 483 DwMmcHcGetCapability ( 484 IN EFI_PCI_IO_PROTOCOL *PciIo, 485 IN EFI_HANDLE Controller, 486 IN UINT8 Slot, 487 OUT DW_MMC_HC_SLOT_CAP *Capability 488 ); 489 490 /** 491 Get the maximum current capability data from the specified slot. 492 493 @param[in] PciIo The PCI IO protocol instance. 494 @param[in] Slot The slot number of the SD card to send the command to. 495 @param[out] MaxCurrent The buffer to store the maximum current capability data. 496 497 @retval EFI_SUCCESS The operation executes successfully. 498 @retval Others The operation fails. 499 500 **/ 501 EFI_STATUS 502 DwMmcHcGetMaxCurrent ( 503 IN EFI_PCI_IO_PROTOCOL *PciIo, 504 IN UINT8 Slot, 505 OUT UINT64 *MaxCurrent 506 ); 507 508 /** 509 Detect whether there is a SD/MMC card attached at the specified SD/MMC host controller 510 slot. 511 512 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details. 513 514 @param[in] PciIo The PCI IO protocol instance. 515 @param[in] Slot The slot number of the SD card to send the command to. 516 @param[out] MediaPresent The pointer to the media present boolean value. 517 518 @retval EFI_SUCCESS There is no media change happened. 519 @retval EFI_MEDIA_CHANGED There is media change happened. 520 @retval Others The detection fails. 521 522 **/ 523 EFI_STATUS 524 DwMmcHcCardDetect ( 525 IN EFI_PCI_IO_PROTOCOL *PciIo, 526 IN EFI_HANDLE Controller, 527 IN UINT8 Slot, 528 OUT BOOLEAN *MediaPresent 529 ); 530 531 /** 532 Stop SD/MMC card clock. 533 534 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details. 535 536 @param[in] PciIo The PCI IO protocol instance. 537 @param[in] Slot The slot number of the SD card to send the command to. 538 539 @retval EFI_SUCCESS Succeed to stop SD/MMC clock. 540 @retval Others Fail to stop SD/MMC clock. 541 542 **/ 543 EFI_STATUS 544 DwMmcHcStopClock ( 545 IN EFI_PCI_IO_PROTOCOL *PciIo, 546 IN UINT8 Slot 547 ); 548 549 /** 550 SD/MMC card clock supply. 551 552 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details. 553 554 @param[in] PciIo The PCI IO protocol instance. 555 @param[in] Slot The slot number of the SD card to send the command to. 556 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz. 557 @param[in] Capability The capability of the slot. 558 559 @retval EFI_SUCCESS The clock is supplied successfully. 560 @retval Others The clock isn't supplied successfully. 561 562 **/ 563 EFI_STATUS 564 DwMmcHcClockSupply ( 565 IN EFI_PCI_IO_PROTOCOL *PciIo, 566 IN UINT8 Slot, 567 IN UINT64 ClockFreq, 568 IN DW_MMC_HC_SLOT_CAP Capability 569 ); 570 571 /** 572 SD/MMC bus power control. 573 574 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details. 575 576 @param[in] PciIo The PCI IO protocol instance. 577 @param[in] Slot The slot number of the SD card to send the command to. 578 @param[in] PowerCtrl The value setting to the power control register. 579 580 @retval TRUE There is a SD/MMC card attached. 581 @retval FALSE There is no a SD/MMC card attached. 582 583 **/ 584 EFI_STATUS 585 DwMmcHcPowerControl ( 586 IN EFI_PCI_IO_PROTOCOL *PciIo, 587 IN UINT8 Slot, 588 IN UINT8 PowerCtrl 589 ); 590 591 /** 592 Set the SD/MMC bus width. 593 594 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details. 595 596 @param[in] PciIo The PCI IO protocol instance. 597 @param[in] Slot The slot number of the SD card to send the command to. 598 @param[in] BusWidth The bus width used by the SD/MMC device, it must be 1, 4 or 8. 599 600 @retval EFI_SUCCESS The bus width is set successfully. 601 @retval Others The bus width isn't set successfully. 602 603 **/ 604 EFI_STATUS 605 DwMmcHcSetBusWidth ( 606 IN EFI_PCI_IO_PROTOCOL *PciIo, 607 IN UINT8 Slot, 608 IN BOOLEAN IsDdr, 609 IN UINT16 BusWidth 610 ); 611 612 /** 613 Supply SD/MMC card with lowest clock frequency at initialization. 614 615 @param[in] PciIo The PCI IO protocol instance. 616 @param[in] Slot The slot number of the SD card to send the command to. 617 @param[in] Capability The capability of the slot. 618 619 @retval EFI_SUCCESS The clock is supplied successfully. 620 @retval Others The clock isn't supplied successfully. 621 622 **/ 623 EFI_STATUS 624 DwMmcHcInitClockFreq ( 625 IN EFI_PCI_IO_PROTOCOL *PciIo, 626 IN UINT8 Slot, 627 IN DW_MMC_HC_SLOT_CAP Capability 628 ); 629 630 /** 631 Supply SD/MMC card with maximum voltage at initialization. 632 633 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details. 634 635 @param[in] PciIo The PCI IO protocol instance. 636 @param[in] Slot The slot number of the SD card to send the command to. 637 @param[in] Capability The capability of the slot. 638 639 @retval EFI_SUCCESS The voltage is supplied successfully. 640 @retval Others The voltage isn't supplied successfully. 641 642 **/ 643 EFI_STATUS 644 DwMmcHcInitPowerVoltage ( 645 IN EFI_PCI_IO_PROTOCOL *PciIo, 646 IN UINT8 Slot, 647 IN DW_MMC_HC_SLOT_CAP Capability 648 ); 649 650 /** 651 Initialize the Timeout Control register with most conservative value at initialization. 652 653 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details. 654 655 @param[in] PciIo The PCI IO protocol instance. 656 @param[in] Slot The slot number of the SD card to send the command to. 657 658 @retval EFI_SUCCESS The timeout control register is configured successfully. 659 @retval Others The timeout control register isn't configured successfully. 660 661 **/ 662 EFI_STATUS 663 DwMmcHcInitTimeoutCtrl ( 664 IN EFI_PCI_IO_PROTOCOL *PciIo, 665 IN UINT8 Slot 666 ); 667 668 /** 669 Initial SD/MMC host controller with lowest clock frequency, max power and max timeout value 670 at initialization. 671 672 @param[in] PciIo The PCI IO protocol instance. 673 @param[in] Slot The slot number of the SD card to send the command to. 674 @param[in] Capability The capability of the slot. 675 676 @retval EFI_SUCCESS The host controller is initialized successfully. 677 @retval Others The host controller isn't initialized successfully. 678 679 **/ 680 EFI_STATUS 681 DwMmcHcInitHost ( 682 IN EFI_PCI_IO_PROTOCOL *PciIo, 683 IN UINT8 Slot, 684 IN DW_MMC_HC_SLOT_CAP Capability 685 ); 686 687 #endif /* _DW_MMC_HCI_H_ */ 688
