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Searched
defs:DefInst
(Results
1 - 12
of
12
) sorted by null
/external/llvm/lib/Target/AMDGPU/
SILowerI1Copies.cpp
110
MachineInstr *
DefInst
= MRI.getUniqueVRegDef(Src.getReg());
111
if (
DefInst
->getOpcode() == AMDGPU::S_MOV_B64) {
112
if (
DefInst
->getOperand(1).isImm()) {
115
int64_t Val =
DefInst
->getOperand(1).getImm();
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
SILowerI1Copies.cpp
106
MachineInstr *
DefInst
= MRI.getUniqueVRegDef(Src.getReg());
111
if (
DefInst
->getOpcode() == AMDGPU::S_MOV_B64) {
112
if (
DefInst
->getOperand(1).isImm()) {
115
int64_t Val =
DefInst
->getOperand(1).getImm();
137
if (
DefInst
->getOpcode() == AMDGPU::V_CNDMASK_B32_e64 &&
138
DefInst
->getOperand(1).isImm() &&
DefInst
->getOperand(2).isImm() &&
139
DefInst
->getOperand(1).getImm() == 0 &&
140
DefInst
->getOperand(2).getImm() != 0 &&
141
DefInst
->getOperand(3).isReg() &
[
all
...]
SIPeepholeSDWA.cpp
529
const MachineInstr *
DefInst
= Def.getParent();
530
if (!TII->isFoldableCopy(*
DefInst
))
533
const MachineOperand &Copied =
DefInst
->getOperand(1);
[
all
...]
/external/deqp-deps/SPIRV-Tools/source/opt/
function.h
54
Instruction&
DefInst
() { return *def_inst_; }
55
const Instruction&
DefInst
() const { return *def_inst_; }
/external/swiftshader/third_party/SPIRV-Tools/source/opt/
function.h
54
Instruction&
DefInst
() { return *def_inst_; }
55
const Instruction&
DefInst
() const { return *def_inst_; }
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
PPCBranchCoalescing.cpp
465
MachineInstr *
DefInst
= MRI->getVRegDef(Use.getReg());
466
if (
DefInst
->isPHI() &&
DefInst
->getParent() == MI.getParent()) {
/external/llvm/lib/Target/Hexagon/
HexagonCopyToCombine.cpp
400
MachineInstr *
DefInst
= LastDef[Reg];
401
if (!
DefInst
)
403
if (!isCombinableInstType(*
DefInst
, TII, ShouldCombineAggressively))
408
MachineBasicBlock::iterator It(
DefInst
);
419
PotentiallyNewifiableTFR.insert(
DefInst
);
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
HexagonCopyToCombine.cpp
415
MachineInstr *
DefInst
= LastDef[Reg];
416
if (!
DefInst
)
418
if (!isCombinableInstType(*
DefInst
, TII, ShouldCombineAggressively))
423
MachineBasicBlock::iterator It(
DefInst
);
434
PotentiallyNewifiableTFR.insert(
DefInst
);
[
all
...]
/external/swiftshader/third_party/subzero/src/
IceRegAlloc.cpp
519
const Inst *
DefInst
= VMetadata->getFirstDefinitionSingleBlock(Iter.Cur);
520
if (
DefInst
== nullptr)
523
assert(
DefInst
->getDest() == Iter.Cur);
525
DefInst
->isVarAssign() && !VMetadata->isMultiDef(Iter.Cur);
526
FOREACH_VAR_IN_INST(SrcVar, *
DefInst
) {
[
all
...]
/external/llvm/lib/Transforms/Scalar/
EarlyCSE.cpp
282
Instruction *
DefInst
;
288
:
DefInst
(nullptr), Generation(0), MatchingId(-1), IsAtomic(false),
292
:
DefInst
(Inst), Generation(Generation), MatchingId(MatchingId),
637
if (InVal.
DefInst
!= nullptr &&
644
Value *Op = getOrCreateResult(InVal.
DefInst
, Inst->getType());
647
<< " to: " << *InVal.
DefInst
<< '\n');
715
if (InVal.
DefInst
&&
716
InVal.
DefInst
== getOrCreateResult(Inst, InVal.
DefInst
->getType()) &&
[
all
...]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/
EarlyCSE.cpp
367
Instruction *
DefInst
= nullptr;
375
:
DefInst
(Inst), Generation(Generation), MatchingId(MatchingId),
[
all
...]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/
MemorySSA.cpp
253
Instruction *
DefInst
= MD->getMemoryInst();
254
assert(
DefInst
&& "Defining instruction not actually an instruction");
258
if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(
DefInst
)) {
283
ModRefInfo I = AA.getModRefInfo(
DefInst
, UseCS);
288
if (auto *DefLoad = dyn_cast<LoadInst>(
DefInst
))
292
ModRefInfo I = AA.getModRefInfo(
DefInst
, UseLoc);
[
all
...]
Completed in 538 milliseconds