/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
BlackfinISelDAGToDAG.cpp | 156 const TargetRegisterClass *DefRC = 164 if (!DefRC || !UseRC) 167 if ((isCC(DefRC) && !isDCC(UseRC)) || (isCC(UseRC) && !isDCC(DefRC))) {
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/external/llvm/lib/CodeGen/ |
DetectDeadLanes.cpp | 376 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); 390 } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) {
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PeepholeOptimizer.cpp | 624 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); 685 ShouldRewrite = TRI->shouldRewriteCopySrc(DefRC, SubReg, SrcRC, [all...] |
RegisterCoalescer.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
DetectDeadLanes.cpp | 374 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); 388 } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) {
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PeepholeOptimizer.cpp | 669 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); 732 if (!TRI->shouldRewriteCopySrc(DefRC, RegSubReg.SubReg, SrcRC, [all...] |
RegisterCoalescer.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
AArch64InstructionSelector.cpp | 723 const TargetRegisterClass *DefRC = nullptr; 725 DefRC = TRI.getRegClass(DefReg); 730 DefRC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>(); 731 if (!DefRC) { 737 DefRC = getRegClassForTypeOnBank(DefTy, RB, RBI); 738 if (!DefRC) { 746 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
X86SpeculativeLoadHardening.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
HexagonConstPropagation.cpp | [all...] |