/external/swiftshader/src/Pipeline/ |
PixelRoutine.hpp | 43 typedef Shader::DestinationParameter Dst;
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/external/swiftshader/src/Shader/ |
PixelRoutine.hpp | 43 typedef Shader::DestinationParameter Dst;
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/external/llvm/include/llvm/Target/ |
CostTable.h | 46 MVT::SimpleValueType Dst; 55 int ISD, MVT Dst, MVT Src) { 59 Dst == Entry.Dst;
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/external/mesa3d/src/gallium/drivers/r300/compiler/ |
radeon_variable.h | 46 struct rc_dst_register Dst;
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
CostTable.h | 47 MVT::SimpleValueType Dst; 56 int ISD, MVT Dst, MVT Src) { 58 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
ConstantFoldingMIRBuilder.h | 82 MachineInstrBuilder buildBinaryOp(unsigned Opcode, unsigned Dst, 84 validateBinaryOp(Dst, Src0, Src1); 87 return buildConstant(Dst, MaybeCst->getSExtValue()); 88 return buildInstr(Opcode).addDef(Dst).addUse(Src0).addUse(Src1); 94 unsigned Dst = getDestFromArg(Ty); 95 return buildInstr(Opc, Dst, getRegFromArg(std::forward<UseArg1Ty>(Arg1)), 101 MachineInstrBuilder buildInstr(unsigned Opc, unsigned Dst, unsigned Src0, 119 return buildBinaryOp(Opc, Dst, Src0, Src1); 122 return buildInstr(Opc).addDef(Dst).addUse(Src0).addUse(Src1);
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/device/linaro/bootloader/edk2/MdeModulePkg/Universal/Network/Ip4Dxe/ |
Ip4Icmp.c | 109 IP4_ADDR Dst;
138 Dst = NTOHL (Icmp->IpHead.Dst);
140 CacheEntry = Ip4FindRouteCache (Ip4Instance->RouteTable, Dst, Src);
257 ReplyHead.Dst = Head->Src;
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Ip4Input.h | 56 // the same (Dst, Src, Id, Protocol).
58 IP4_ADDR Dst;
83 #define IP4_ASSEMBLE_HASH(Dst, Src, Id, Proto) \
84 (((Dst) + (Src) + ((Id) << 16) + (Proto)) % IP4_ASSEMLE_HASH_SIZE)
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/external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
AMDGPUAsmBackend.cpp | 105 uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset()); 106 *Dst = BrImm;
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/external/llvm/lib/Target/Lanai/ |
LanaiFrameLowering.cpp | 76 unsigned Dst = MI.getOperand(0).getReg(); 79 BuildMI(*MBB, MI, DL, LII.get(Lanai::ADD_I_LO), Dst)
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/external/swiftshader/third_party/LLVM/lib/CodeGen/AsmPrinter/ |
AsmPrinterDwarf.cpp | 213 const MachineLocation &Dst = Move.getDestination(); 217 if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) { 226 assert(Dst.isReg() && "Machine move not supported yet."); 227 OutStreamer.EmitCFIDefCfaRegister(RI->getDwarfRegNum(Dst.getReg(), true)); 229 assert(!Dst.isReg() && "Machine move not supported yet."); 231 Dst.getOffset());
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
LanaiFrameLowering.cpp | 76 unsigned Dst = MI.getOperand(0).getReg(); 79 BuildMI(*MBB, MI, DL, LII.get(Lanai::ADD_I_LO), Dst)
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/frameworks/av/media/libmedia/include/media/ |
convert.h | 193 typedef std::vector<DstElem> Dst; 195 static inline bool run(Src &src, Dst &dst) 198 dst.clear(); 199 dst.reserve(src.size()); 205 dst.push_back(dstElem);
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/external/libchrome/base/numerics/ |
clamped_math.h | 53 template <typename Dst> 54 constexpr ClampedNumeric<typename UnderlyingType<Dst>::type> Cast() const { 163 template <typename Dst> 164 constexpr operator Dst() const { 165 return saturated_cast<typename ArithmeticOrUnderlyingEnum<Dst>::type>(
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safe_conversions.h | 27 template <typename Dst, typename Src> 30 static constexpr Dst Do(Src) { 32 return CheckOnFailure::template HandleFailure<Dst>(); 40 template <typename Dst, typename Src, typename Enable = void> 50 template <typename Dst, typename Src> 52 Dst, 55 std::is_integral<Dst>::value && std::is_integral<Src>::value && 56 std::is_signed<Dst>::value && std::is_signed<Src>::value && 57 !IsTypeInRangeForNumericType<Dst, Src>::value>::type> { 63 return value == static_cast<Dst>(value) [all...] |
/external/llvm/lib/Target/AMDGPU/ |
SILowerI1Copies.cpp | 95 const MachineOperand &Dst = MI.getOperand(0); 99 !TargetRegisterInfo::isVirtualRegister(Dst.getReg())) 102 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg()); 107 I1Defs.push_back(Dst.getReg()); 113 I1Defs.push_back(Dst.getReg()); 119 .addOperand(Dst) 127 .addOperand(Dst) 135 .addOperand(Dst)
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/external/llvm/lib/Target/ARM/InstPrinter/ |
ARMInstPrinter.cpp | 80 const MCOperand &Dst = MI->getOperand(0); 90 printRegName(O, Dst.getReg()); 103 const MCOperand &Dst = MI->getOperand(0); 112 printRegName(O, Dst.getReg()); [all...] |
/external/pdfium/third_party/base/numerics/ |
safe_conversions.h | 53 template <typename Dst, typename Src> 55 return internal::DstRangeRelationToSrcRange<Dst>(value).IsValid(); 74 template <typename Dst, class CheckHandler = CheckOnFailure, typename Src> 75 constexpr Dst checked_cast(Src value) { 79 return IsValueInRangeForNumericType<Dst, SrcType>(value) 80 ? static_cast<Dst>(static_cast<SrcType>(value)) 81 : CheckHandler::template HandleFailure<Dst>(); 108 template <typename Dst, template <typename> class S, typename Src> 109 constexpr Dst saturated_cast_impl(Src value, RangeCheck constraint) { 113 ? (!constraint.IsUnderflowFlagSet() ? static_cast<Dst>(value [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
SILowerI1Copies.cpp | 95 const MachineOperand &Dst = MI.getOperand(0); 99 !TargetRegisterInfo::isVirtualRegister(Dst.getReg())) 102 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg()); 109 I1Defs.push_back(Dst.getReg()); 113 I1Defs.push_back(Dst.getReg()); 119 .add(Dst) 130 .add(Dst) 149 .add(Dst) 154 .add(Dst)
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/InstPrinter/ |
ARMInstPrinter.cpp | 88 const MCOperand &Dst = MI->getOperand(0); 98 printRegName(O, Dst.getReg()); 111 const MCOperand &Dst = MI->getOperand(0); 120 printRegName(O, Dst.getReg()); [all...] |
/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseUefiDecompressLib/ |
BaseUefiDecompressLib.c | 779 UINT8 *Dst;
786 Dst = Destination;
812 Sd->mDstBase = Dst;
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/device/linaro/bootloader/edk2/MdePkg/Library/BaseUefiDecompressLib/ |
BaseUefiDecompressLib.c | 748 UINT8 *Dst;
755 Dst = Destination;
778 Sd->mDstBase = Dst;
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/device/linaro/bootloader/edk2/NetworkPkg/Ip6Dxe/ |
Ip6Input.h | 37 #define IP6_ASSEMBLE_HASH(Dst, Src, Id) \
38 ((*((UINT32 *) (Dst)) + *((UINT32 *) (Src)) + (Id)) % IP6_ASSEMLE_HASH_SIZE)
77 // the same (Dst, Src, Id).
79 EFI_IPv6_ADDRESS Dst;
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/external/llvm/lib/IR/ |
GCOV.cpp | 181 uint32_t Dst; 182 if (!Buff.readInt(Dst)) 184 Edges.push_back(make_unique<GCOVEdge>(*Blocks[BlockNo], *Blocks[Dst])); 187 Blocks[Dst]->addSrcEdge(Edge); 384 if (!DstEdges[DstEdgeNo]->Dst.getNumDstEdges()) 385 DstEdges[DstEdgeNo]->Dst.Counter += N; 416 dbgs() << Edge->Dst.Number << " (" << Edge->Count << "), ";
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/external/llvm/lib/Support/ |
ConvertUTFWrapper.cpp | 118 UTF8 *Dst = reinterpret_cast<UTF8 *>(&Out[0]); 119 UTF8 *DstEnd = Dst + Out.size(); 122 ConvertUTF16toUTF8(&Src, SrcEnd, &Dst, DstEnd, strictConversion); 130 Out.resize(reinterpret_cast<char *>(Dst) - &Out[0]); 163 UTF16 *Dst = &DstUTF16[0]; 164 UTF16 *DstEnd = Dst + DstUTF16.size(); 167 ConvertUTF8toUTF16(&Src, SrcEnd, &Dst, DstEnd, strictConversion); 175 DstUTF16.resize(Dst - &DstUTF16[0]);
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