/external/llvm/lib/CodeGen/ |
RegisterCoalescer.h | 39 unsigned DstIdx; 61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), 68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), 106 unsigned getDstIdx() const { return DstIdx; }
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TwoAddressInstructionPass.cpp | 132 unsigned SrcIdx, unsigned DstIdx, [all...] |
RegisterCoalescer.cpp | 315 SrcIdx = DstIdx = 0; 362 SrcIdx, DstIdx); 371 DstIdx = SrcSub; 384 if (DstIdx && !SrcIdx) { 386 std::swap(SrcIdx, DstIdx); 405 std::swap(SrcIdx, DstIdx); 429 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); 444 TRI.composeSubRegIndices(DstIdx, DstSub); [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
RegisterCoalescer.h | 38 unsigned DstIdx = 0; 102 unsigned getDstIdx() const { return DstIdx; }
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TwoAddressInstructionPass.cpp | 137 bool commuteInstruction(MachineInstr *MI, unsigned DstIdx, 157 unsigned SrcIdx, unsigned DstIdx, 683 unsigned DstIdx, 704 unsigned RegA = MI->getOperand(DstIdx).getReg(); [all...] |
RegisterCoalescer.cpp | 349 SrcIdx = DstIdx = 0; 396 SrcIdx, DstIdx); 405 DstIdx = SrcSub; 418 if (DstIdx && !SrcIdx) { 420 std::swap(SrcIdx, DstIdx); 439 std::swap(SrcIdx, DstIdx); 463 assert(!DstIdx && !SrcIdx && "Inconsistent CoalescerPair state."); 478 TRI.composeSubRegIndices(DstIdx, DstSub); [all...] |
/external/llvm/lib/Target/AMDGPU/ |
R600ExpandSpecialInstrs.cpp | 83 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); 84 assert(DstIdx != -1); 85 MachineOperand &DstOp = MI.getOperand(DstIdx);
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R600Packetizer.cpp | 92 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst); 93 if (DstIdx == -1) { 96 unsigned Dst = BI->getOperand(DstIdx).getReg();
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R600ISelLowering.cpp | 223 int DstIdx = TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::dst); 224 assert(DstIdx != -1); 228 if (!MRI.use_empty(MI.getOperand(DstIdx).getReg()) || [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
R600ExpandSpecialInstrs.cpp | 99 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); 100 assert(DstIdx != -1); 101 MachineOperand &DstOp = MI.getOperand(DstIdx);
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R600Packetizer.cpp | 90 int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst); 91 if (DstIdx == -1) { 94 unsigned Dst = BI->getOperand(DstIdx).getReg();
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SIPeepholeSDWA.cpp | 406 auto DstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 408 auto TiedIdx = MI.findTiedOperandIdx(DstIdx); [all...] |
R600ISelLowering.cpp | 302 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); 303 assert(DstIdx != -1); 307 if (!MRI.use_empty(MI.getOperand(DstIdx).getReg()) || [all...] |
SIInstrInfo.cpp | [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
TwoAddressInstructionPass.cpp | 126 unsigned SrcIdx, unsigned DstIdx, 864 unsigned SrcIdx, unsigned DstIdx, unsigned Dist [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrInfo.cpp | [all...] |
X86ISelLowering.cpp | [all...] |
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/AsmParser/ |
AMDGPUAsmParser.cpp | [all...] |