1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015 Freescale Semiconductor, Inc. 4 * 5 * Author: 6 * Peng Fan <Peng.Fan (at) freescale.com> 7 */ 8 9 #ifndef __ARCH_ARM_MACH_MX7_CCM_REGS_H__ 10 #define __ARCH_ARM_MACH_MX7_CCM_REGS_H__ 11 12 #include <asm/arch/imx-regs.h> 13 #include <asm/io.h> 14 15 #define CCM_GPR0_OFFSET 0x0 16 #define CCM_OBSERVE0_OFFSET 0x0400 17 #define CCM_SCTRL0_OFFSET 0x0800 18 #define CCM_CCGR0_OFFSET 0x4000 19 #define CCM_ROOT0_TARGET_OFFSET 0x8000 20 21 #ifndef __ASSEMBLY__ 22 23 struct mxc_ccm_ccgr { 24 uint32_t ccgr; 25 uint32_t ccgr_set; 26 uint32_t ccgr_clr; 27 uint32_t ccgr_tog; 28 }; 29 30 struct mxc_ccm_root_slice { 31 uint32_t target_root; 32 uint32_t target_root_set; 33 uint32_t target_root_clr; 34 uint32_t target_root_tog; 35 uint32_t reserved_0[4]; 36 uint32_t post; 37 uint32_t post_root_set; 38 uint32_t post_root_clr; 39 uint32_t post_root_tog; 40 uint32_t pre; 41 uint32_t pre_root_set; 42 uint32_t pre_root_clr; 43 uint32_t pre_root_tog; 44 uint32_t reserved_1[12]; 45 uint32_t access_ctrl; 46 uint32_t access_ctrl_root_set; 47 uint32_t access_ctrl_root_clr; 48 uint32_t access_ctrl_root_tog; 49 }; 50 51 /** CCM - Peripheral register structure */ 52 struct mxc_ccm_reg { 53 uint32_t gpr0; 54 uint32_t gpr0_set; 55 uint32_t gpr0_clr; 56 uint32_t gpr0_tog; 57 uint32_t reserved_0[4092]; 58 struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */ 59 uint32_t reserved_1[3332]; 60 struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */ 61 62 }; 63 64 struct mxc_ccm_anatop_reg { 65 uint32_t ctrl_24m; /* offset 0x0000 */ 66 uint32_t ctrl_24m_set; 67 uint32_t ctrl_24m_clr; 68 uint32_t ctrl_24m_tog; 69 uint32_t rcosc_config0; /* offset 0x0010 */ 70 uint32_t rcosc_config0_set; 71 uint32_t rcosc_config0_clr; 72 uint32_t rcosc_config0_tog; 73 uint32_t rcosc_config1; /* offset 0x0020 */ 74 uint32_t rcosc_config1_set; 75 uint32_t rcosc_config1_clr; 76 uint32_t rcosc_config1_tog; 77 uint32_t rcosc_config2; /* offset 0x0030 */ 78 uint32_t rcosc_config2_set; 79 uint32_t rcosc_config2_clr; 80 uint32_t rcosc_config2_tog; 81 uint8_t reserved_0[16]; 82 uint32_t osc_32k; /* offset 0x0050 */ 83 uint32_t osc_32k_set; 84 uint32_t osc_32k_clr; 85 uint32_t osc_32k_tog; 86 uint32_t pll_arm; /* offset 0x0060 */ 87 uint32_t pll_arm_set; 88 uint32_t pll_arm_clr; 89 uint32_t pll_arm_tog; 90 uint32_t pll_ddr; /* offset 0x0070 */ 91 uint32_t pll_ddr_set; 92 uint32_t pll_ddr_clr; 93 uint32_t pll_ddr_tog; 94 uint32_t pll_ddr_ss; /* offset 0x0080 */ 95 uint8_t reserved_1[12]; 96 uint32_t pll_ddr_num; /* offset 0x0090 */ 97 uint8_t reserved_2[12]; 98 uint32_t pll_ddr_denom; /* offset 0x00a0 */ 99 uint8_t reserved_3[12]; 100 uint32_t pll_480; /* offset 0x00b0 */ 101 uint32_t pll_480_set; 102 uint32_t pll_480_clr; 103 uint32_t pll_480_tog; 104 uint32_t pfd_480a; /* offset 0x00c0 */ 105 uint32_t pfd_480a_set; 106 uint32_t pfd_480a_clr; 107 uint32_t pfd_480a_tog; 108 uint32_t pfd_480b; /* offset 0x00d0 */ 109 uint32_t pfd_480b_set; 110 uint32_t pfd_480b_clr; 111 uint32_t pfd_480b_tog; 112 uint32_t pll_enet; /* offset 0x00e0 */ 113 uint32_t pll_enet_set; 114 uint32_t pll_enet_clr; 115 uint32_t pll_enet_tog; 116 uint32_t pll_audio; /* offset 0x00f0 */ 117 uint32_t pll_audio_set; 118 uint32_t pll_audio_clr; 119 uint32_t pll_audio_tog; 120 uint32_t pll_audio_ss; /* offset 0x0100 */ 121 uint8_t reserved_4[12]; 122 uint32_t pll_audio_num; /* offset 0x0110 */ 123 uint8_t reserved_5[12]; 124 uint32_t pll_audio_denom; /* offset 0x0120 */ 125 uint8_t reserved_6[12]; 126 uint32_t pll_video; /* offset 0x0130 */ 127 uint32_t pll_video_set; 128 uint32_t pll_video_clr; 129 uint32_t pll_video_tog; 130 uint32_t pll_video_ss; /* offset 0x0140 */ 131 uint8_t reserved_7[12]; 132 uint32_t pll_video_num; /* offset 0x0150 */ 133 uint8_t reserved_8[12]; 134 uint32_t pll_video_denom; /* offset 0x0160 */ 135 uint8_t reserved_9[12]; 136 uint32_t clk_misc0; /* offset 0x0170 */ 137 uint32_t clk_misc0_set; 138 uint32_t clk_misc0_clr; 139 uint32_t clk_misc0_tog; 140 uint32_t clk_rsvd; /* offset 0x0180 */ 141 uint8_t reserved_10[124]; 142 uint32_t reg_1p0a; /* offset 0x0200 */ 143 uint32_t reg_1p0a_set; 144 uint32_t reg_1p0a_clr; 145 uint32_t reg_1p0a_tog; 146 uint32_t reg_1p0d; /* offsest 0x0210 */ 147 uint32_t reg_1p0d_set; 148 uint32_t reg_1p0d_clr; 149 uint32_t reg_1p0d_tog; 150 uint32_t reg_hsic_1p2; /* offset 0x0220 */ 151 uint32_t reg_hsic_1p2_set; 152 uint32_t reg_hsic_1p2_clr; 153 uint32_t reg_hsic_1p2_tog; 154 uint32_t reg_lpsr_1p0; /* offset 0x0230 */ 155 uint32_t reg_lpsr_1p0_set; 156 uint32_t reg_lpsr_1p0_clr; 157 uint32_t reg_lpsr_1p0_tog; 158 uint32_t reg_3p0; /* offset 0x0240 */ 159 uint32_t reg_3p0_set; 160 uint32_t reg_3p0_clr; 161 uint32_t reg_3p0_tog; 162 uint32_t reg_snvs; /* offset 0x0250 */ 163 uint32_t reg_snvs_set; 164 uint32_t reg_snvs_clr; 165 uint32_t reg_snvs_tog; 166 uint32_t analog_debug_misc0; /* offset 0x0260 */ 167 uint32_t analog_debug_misc0_set; 168 uint32_t analog_debug_misc0_clr; 169 uint32_t analog_debug_misc0_tog; 170 uint32_t ref; /* offset 0x0270 */ 171 uint32_t ref_set; 172 uint32_t ref_clr; 173 uint32_t ref_tog; 174 uint8_t reserved_11[128]; 175 uint32_t tempsense0; /* offset 0x0300 */ 176 uint32_t tempsense0_set; 177 uint32_t tempsense0_clr; 178 uint32_t tempsense0_tog; 179 uint32_t tempsense1; /* offset 0x0310 */ 180 uint32_t tempsense1_set; 181 uint32_t tempsense1_clr; 182 uint32_t tempsense1_tog; 183 uint32_t tempsense_trim; /* offset 0x0320 */ 184 uint32_t tempsense_trim_set; 185 uint32_t tempsense_trim_clr; 186 uint32_t tempsense_trim_tog; 187 uint32_t lowpwr_ctrl; /* offset 0x0330 */ 188 uint32_t lowpwr_ctrl_set; 189 uint32_t lowpwr_ctrl_clr; 190 uint32_t lowpwr_ctrl_tog; 191 uint32_t snvs_tamper_offset_ctrl; /* offset 0x0340 */ 192 uint32_t snvs_tamper_offset_ctrl_set; 193 uint32_t snvs_tamper_offset_ctrl_clr; 194 uint32_t snvs_tamper_offset_ctrl_tog; 195 uint32_t snvs_tamper_pull_ctrl; /* offset 0x0350 */ 196 uint32_t snvs_tamper_pull_ctrl_set; 197 uint32_t snvs_tamper_pull_ctrl_clr; 198 uint32_t snvs_tamper_pull_ctrl_tog; 199 uint32_t snvs_test; /* offset 0x0360 */ 200 uint32_t snvs_test_set; 201 uint32_t snvs_test_clr; 202 uint32_t snvs_test_tog; 203 uint32_t snvs_tamper_trim_ctrl; /* offset 0x0370 */ 204 uint32_t snvs_tamper_trim_ctrl_set; 205 uint32_t snvs_tamper_trim_ctrl_ctrl; 206 uint32_t snvs_tamper_trim_ctrl_tog; 207 uint32_t snvs_misc_ctrl; /* offset 0x0380 */ 208 uint32_t snvs_misc_ctrl_set; 209 uint32_t snvs_misc_ctrl_clr; 210 uint32_t snvs_misc_ctrl_tog; 211 uint8_t reserved_12[112]; 212 uint32_t misc; /* offset 0x0400 */ 213 uint8_t reserved_13[252]; 214 uint32_t adc0; /* offset 0x0500 */ 215 uint8_t reserved_14[12]; 216 uint32_t adc1; /* offset 0x0510 */ 217 uint8_t reserved_15[748]; 218 uint32_t digprog; /* offset 0x0800 */ 219 }; 220 #endif 221 222 #define ANADIG_CLK_MISC0_PFD_480_AUTOGATE_EN_MASK (0x01 << 17) 223 224 #define ANADIG_PLL_LOCK 0x80000000 225 226 #define ANADIG_PLL_ARM_PWDN_MASK (0x01 << 12) 227 #define ANADIG_PLL_480_PWDN_MASK (0x01 << 12) 228 #define ANADIG_PLL_DDR_PWDN_MASK (0x01 << 20) 229 #define ANADIG_PLL_ENET_PWDN_MASK (0x01 << 5) 230 #define ANADIG_PLL_VIDEO_PWDN_MASK (0x01 << 12) 231 232 233 #define ANATOP_PFD480B_PFD4_FRAC_MASK 0x0000003f 234 #define ANATOP_PFD480B_PFD4_FRAC_320M_VAL 0x0000001B 235 #define ANATOP_PFD480B_PFD4_FRAC_392M_VAL 0x00000016 236 #define ANATOP_PFD480B_PFD4_FRAC_432M_VAL 0x00000014 237 238 /* PLL_ARM Bit Fields */ 239 #define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK 0x7F 240 #define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT 0 241 #define CCM_ANALOG_PLL_ARM_HALF_LF_MASK 0x80 242 #define CCM_ANALOG_PLL_ARM_HALF_LF_SHIFT 7 243 #define CCM_ANALOG_PLL_ARM_DOUBLE_LF_MASK 0x100 244 #define CCM_ANALOG_PLL_ARM_DOUBLE_LF_SHIFT 8 245 #define CCM_ANALOG_PLL_ARM_HALF_CP_MASK 0x200 246 #define CCM_ANALOG_PLL_ARM_HALF_CP_SHIFT 9 247 #define CCM_ANALOG_PLL_ARM_DOUBLE_CP_MASK 0x400 248 #define CCM_ANALOG_PLL_ARM_DOUBLE_CP_SHIFT 10 249 #define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_MASK 0x800 250 #define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_SHIFT 11 251 #define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK 0x1000 252 #define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT 12 253 #define CCM_ANALOG_PLL_ARM_ENABLE_CLK_MASK 0x2000 254 #define CCM_ANALOG_PLL_ARM_ENABLE_CLK_SHIFT 13 255 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK 0xC000 256 #define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT 14 257 #define CCM_ANALOG_PLL_ARM_BYPASS_MASK 0x10000 258 #define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT 16 259 #define CCM_ANALOG_PLL_ARM_LVDS_SEL_MASK 0x20000 260 #define CCM_ANALOG_PLL_ARM_LVDS_SEL_SHIFT 17 261 #define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_MASK 0x40000 262 #define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_SHIFT 18 263 #define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK 0x80000 264 #define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT 19 265 #define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_MASK 0x100000 266 #define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_SHIFT 20 267 #define CCM_ANALOG_PLL_ARM_RSVD0_MASK 0x7FE00000 268 #define CCM_ANALOG_PLL_ARM_RSVD0_SHIFT 21 269 #define CCM_ANALOG_PLL_ARM_LOCK_MASK 0x80000000 270 #define CCM_ANALOG_PLL_ARM_LOCK_SHIFT 31 271 272 /* PLL_DDR Bit Fields */ 273 #define CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK 0x7F 274 #define CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT 0 275 #define CCM_ANALOG_PLL_DDR_HALF_LF_MASK 0x80 276 #define CCM_ANALOG_PLL_DDR_HALF_LF_SHIFT 7 277 #define CCM_ANALOG_PLL_DDR_DOUBLE_LF_MASK 0x100 278 #define CCM_ANALOG_PLL_DDR_DOUBLE_LF_SHIFT 8 279 #define CCM_ANALOG_PLL_DDR_HALF_CP_MASK 0x200 280 #define CCM_ANALOG_PLL_DDR_HALF_CP_SHIFT 9 281 #define CCM_ANALOG_PLL_DDR_DOUBLE_CP_MASK 0x400 282 #define CCM_ANALOG_PLL_DDR_DOUBLE_CP_SHIFT 10 283 #define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_MASK 0x800 284 #define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_SHIFT 11 285 #define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK 0x1000 286 #define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_SHIFT 12 287 #define CCM_ANALOG_PLL_DDR_ENABLE_CLK_MASK 0x2000 288 #define CCM_ANALOG_PLL_DDR_ENABLE_CLK_SHIFT 13 289 #define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_MASK 0xC000 290 #define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_SHIFT 14 291 #define CCM_ANALOG_PLL_DDR_BYPASS_MASK 0x10000 292 #define CCM_ANALOG_PLL_DDR_BYPASS_SHIFT 16 293 #define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_MASK 0x20000 294 #define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_SHIFT 17 295 #define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_MASK 0x40000 296 #define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_SHIFT 18 297 #define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_MASK 0x80000 298 #define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_SHIFT 19 299 #define CCM_ANALOG_PLL_DDR_POWERDOWN_MASK 0x100000 300 #define CCM_ANALOG_PLL_DDR_POWERDOWN_SHIFT 20 301 #define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_MASK 0x600000 302 #define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_SHIFT 21 303 #define CCM_ANALOG_PLL_DDR_RSVD1_MASK 0x7F800000 304 #define CCM_ANALOG_PLL_DDR_RSVD1_SHIFT 23 305 #define CCM_ANALOG_PLL_DDR_LOCK_MASK 0x80000000 306 #define CCM_ANALOG_PLL_DDR_LOCK_SHIFT 31 307 308 /* PLL_480 Bit Fields */ 309 #define CCM_ANALOG_PLL_480_DIV_SELECT_MASK 0x1 310 #define CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT 0 311 #define CCM_ANALOG_PLL_480_RSVD0_MASK 0xE 312 #define CCM_ANALOG_PLL_480_RSVD0_SHIFT 1 313 #define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK 0x10 314 #define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_SHIFT 4 315 #define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK 0x20 316 #define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_SHIFT 5 317 #define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK 0x40 318 #define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_SHIFT 6 319 #define CCM_ANALOG_PLL_480_HALF_LF_MASK 0x80 320 #define CCM_ANALOG_PLL_480_HALF_LF_SHIFT 7 321 #define CCM_ANALOG_PLL_480_DOUBLE_LF_MASK 0x100 322 #define CCM_ANALOG_PLL_480_DOUBLE_LF_SHIFT 8 323 #define CCM_ANALOG_PLL_480_HALF_CP_MASK 0x200 324 #define CCM_ANALOG_PLL_480_HALF_CP_SHIFT 9 325 #define CCM_ANALOG_PLL_480_DOUBLE_CP_MASK 0x400 326 #define CCM_ANALOG_PLL_480_DOUBLE_CP_SHIFT 10 327 #define CCM_ANALOG_PLL_480_HOLD_RING_OFF_MASK 0x800 328 #define CCM_ANALOG_PLL_480_HOLD_RING_OFF_SHIFT 11 329 #define CCM_ANALOG_PLL_480_POWERDOWN_MASK 0x1000 330 #define CCM_ANALOG_PLL_480_POWERDOWN_SHIFT 12 331 #define CCM_ANALOG_PLL_480_ENABLE_CLK_MASK 0x2000 332 #define CCM_ANALOG_PLL_480_ENABLE_CLK_SHIFT 13 333 #define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_MASK 0xC000 334 #define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_SHIFT 14 335 #define CCM_ANALOG_PLL_480_BYPASS_MASK 0x10000 336 #define CCM_ANALOG_PLL_480_BYPASS_SHIFT 16 337 #define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_MASK 0x20000 338 #define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_SHIFT 17 339 #define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_MASK 0x40000 340 #define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_SHIFT 18 341 #define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_MASK 0x80000 342 #define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_SHIFT 19 343 #define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_MASK 0x100000 344 #define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_SHIFT 20 345 #define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_MASK 0x200000 346 #define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_SHIFT 21 347 #define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_MASK 0x400000 348 #define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_SHIFT 22 349 #define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_MASK 0x800000 350 #define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_SHIFT 23 351 #define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_MASK 0x1000000 352 #define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_SHIFT 24 353 #define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_MASK 0x2000000 354 #define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_SHIFT 25 355 #define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK 0x4000000 356 #define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_SHIFT 26 357 #define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK 0x8000000 358 #define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_SHIFT 27 359 #define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK 0x10000000 360 #define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_SHIFT 28 361 #define CCM_ANALOG_PLL_480_RSVD1_MASK 0x60000000 362 #define CCM_ANALOG_PLL_480_RSVD1_SHIFT 29 363 #define CCM_ANALOG_PLL_480_LOCK_MASK 0x80000000 364 #define CCM_ANALOG_PLL_480_LOCK_SHIFT 31 365 366 /* PFD_480A Bit Fields */ 367 #define CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK 0x3F 368 #define CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT 0 369 #define CCM_ANALOG_PFD_480A_PFD0_STABLE_MASK 0x40 370 #define CCM_ANALOG_PFD_480A_PFD0_STABLE_SHIFT 6 371 #define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK 0x80 372 #define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_SHIFT 7 373 #define CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK 0x3F00 374 #define CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT 8 375 #define CCM_ANALOG_PFD_480A_PFD1_STABLE_MASK 0x4000 376 #define CCM_ANALOG_PFD_480A_PFD1_STABLE_SHIFT 14 377 #define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK 0x8000 378 #define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_SHIFT 15 379 #define CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK 0x3F0000 380 #define CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT 16 381 #define CCM_ANALOG_PFD_480A_PFD2_STABLE_MASK 0x400000 382 #define CCM_ANALOG_PFD_480A_PFD2_STABLE_SHIFT 22 383 #define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK 0x800000 384 #define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_SHIFT 23 385 #define CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK 0x3F000000 386 #define CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT 24 387 #define CCM_ANALOG_PFD_480A_PFD3_STABLE_MASK 0x40000000 388 #define CCM_ANALOG_PFD_480A_PFD3_STABLE_SHIFT 30 389 #define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK 0x80000000 390 #define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_SHIFT 31 391 /* PFD_480B Bit Fields */ 392 #define CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK 0x3F 393 #define CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT 0 394 #define CCM_ANALOG_PFD_480B_PFD4_STABLE_MASK 0x40 395 #define CCM_ANALOG_PFD_480B_PFD4_STABLE_SHIFT 6 396 #define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK 0x80 397 #define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_SHIFT 7 398 #define CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK 0x3F00 399 #define CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT 8 400 #define CCM_ANALOG_PFD_480B_PFD5_STABLE_MASK 0x4000 401 #define CCM_ANALOG_PFD_480B_PFD5_STABLE_SHIFT 14 402 #define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK 0x8000 403 #define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_SHIFT 15 404 #define CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK 0x3F0000 405 #define CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT 16 406 #define CCM_ANALOG_PFD_480B_PFD6_STABLE_MASK 0x400000 407 #define CCM_ANALOG_PFD_480B_PFD6_STABLE_SHIFT 22 408 #define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK 0x800000 409 #define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_SHIFT 23 410 #define CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK 0x3F000000 411 #define CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT 24 412 #define CCM_ANALOG_PFD_480B_PFD7_STABLE_MASK 0x40000000 413 #define CCM_ANALOG_PFD_480B_PFD7_STABLE_SHIFT 30 414 #define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK 0x80000000 415 #define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_SHIFT 31 416 417 /* PLL_ENET Bit Fields */ 418 #define CCM_ANALOG_PLL_ENET_HALF_LF_MASK 0x1 419 #define CCM_ANALOG_PLL_ENET_HALF_LF_SHIFT 0 420 #define CCM_ANALOG_PLL_ENET_DOUBLE_LF_MASK 0x2 421 #define CCM_ANALOG_PLL_ENET_DOUBLE_LF_SHIFT 1 422 #define CCM_ANALOG_PLL_ENET_HALF_CP_MASK 0x4 423 #define CCM_ANALOG_PLL_ENET_HALF_CP_SHIFT 2 424 #define CCM_ANALOG_PLL_ENET_DOUBLE_CP_MASK 0x8 425 #define CCM_ANALOG_PLL_ENET_DOUBLE_CP_SHIFT 3 426 #define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_MASK 0x10 427 #define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_SHIFT 4 428 #define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK 0x20 429 #define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT 5 430 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK 0x40 431 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_SHIFT 6 432 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK 0x80 433 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_SHIFT 7 434 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK 0x100 435 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_SHIFT 8 436 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK 0x200 437 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_SHIFT 9 438 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK 0x400 439 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_SHIFT 10 440 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK 0x800 441 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_SHIFT 11 442 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK 0x1000 443 #define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_SHIFT 12 444 #define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_MASK 0x2000 445 #define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_SHIFT 13 446 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK 0xC000 447 #define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT 14 448 #define CCM_ANALOG_PLL_ENET_BYPASS_MASK 0x10000 449 #define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT 16 450 #define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_MASK 0x20000 451 #define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_SHIFT 17 452 #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK 0x40000 453 #define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT 18 454 #define CCM_ANALOG_PLL_ENET_RSVD1_MASK 0x7FF80000 455 #define CCM_ANALOG_PLL_ENET_RSVD1_SHIFT 19 456 #define CCM_ANALOG_PLL_ENET_LOCK_MASK 0x80000000 457 #define CCM_ANALOG_PLL_ENET_LOCK_SHIFT 31 458 459 /* PLL_AUDIO Bit Fields */ 460 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK 0x7Fu 461 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT 0 462 #define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) 463 #define CCM_ANALOG_PLL_AUDIO_HALF_LF_MASK 0x80u 464 #define CCM_ANALOG_PLL_AUDIO_HALF_LF_SHIFT 7 465 #define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_MASK 0x100u 466 #define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_SHIFT 8 467 #define CCM_ANALOG_PLL_AUDIO_HALF_CP_MASK 0x200u 468 #define CCM_ANALOG_PLL_AUDIO_HALF_CP_SHIFT 9 469 #define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_MASK 0x400u 470 #define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_SHIFT 10 471 #define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_MASK 0x800u 472 #define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_SHIFT 11 473 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK 0x1000u 474 #define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT 12 475 #define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_MASK 0x2000u 476 #define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_SHIFT 13 477 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK 0xC000u 478 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT 14 479 #define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK) 480 #define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK 0x10000u 481 #define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT 16 482 #define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_MASK 0x20000u 483 #define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_SHIFT 17 484 #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK 0x40000u 485 #define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT 18 486 #define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK 0x180000u 487 #define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT 19 488 #define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK) 489 #define CCM_ANALOG_PLL_AUDIO_RSVD0_MASK 0x200000u 490 #define CCM_ANALOG_PLL_AUDIO_RSVD0_SHIFT 21 491 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK 0xC00000u 492 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT 22 493 #define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK) 494 #define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_MASK 0x1000000u 495 #define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_SHIFT 24 496 #define CCM_ANALOG_PLL_AUDIO_RSVD1_MASK 0x7E000000u 497 #define CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT 25 498 #define CCM_ANALOG_PLL_AUDIO_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_RSVD1_MASK) 499 #define CCM_ANALOG_PLL_AUDIO_LOCK_MASK 0x80000000u 500 #define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT 31 501 /* PLL_AUDIO_SET Bit Fields */ 502 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK 0x7Fu 503 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT 0 504 #define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK) 505 #define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_MASK 0x80u 506 #define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_SHIFT 7 507 #define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_MASK 0x100u 508 #define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_SHIFT 8 509 #define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_MASK 0x200u 510 #define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_SHIFT 9 511 #define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_MASK 0x400u 512 #define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_SHIFT 10 513 #define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_MASK 0x800u 514 #define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_SHIFT 11 515 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK 0x1000u 516 #define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT 12 517 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_MASK 0x2000u 518 #define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_SHIFT 13 519 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK 0xC000u 520 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT 14 521 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK) 522 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK 0x10000u 523 #define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT 16 524 #define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_MASK 0x20000u 525 #define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_SHIFT 17 526 #define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK 0x40000u 527 #define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT 18 528 #define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK 0x180000u 529 #define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT 19 530 #define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK) 531 #define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_MASK 0x200000u 532 #define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_SHIFT 21 533 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK 0xC00000u 534 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT 22 535 #define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK) 536 #define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_MASK 0x1000000u 537 #define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_SHIFT 24 538 #define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK 0x7E000000u 539 #define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT 25 540 #define CCM_ANALOG_PLL_AUDIO_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK) 541 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK 0x80000000u 542 #define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT 31 543 /* PLL_AUDIO_CLR Bit Fields */ 544 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK 0x7Fu 545 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT 0 546 #define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK) 547 #define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_MASK 0x80u 548 #define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_SHIFT 7 549 #define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_MASK 0x100u 550 #define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_SHIFT 8 551 #define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_MASK 0x200u 552 #define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_SHIFT 9 553 #define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_MASK 0x400u 554 #define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_SHIFT 10 555 #define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_MASK 0x800u 556 #define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_SHIFT 11 557 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK 0x1000u 558 #define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT 12 559 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_MASK 0x2000u 560 #define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_SHIFT 13 561 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK 0xC000u 562 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT 14 563 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK) 564 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK 0x10000u 565 #define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT 16 566 #define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_MASK 0x20000u 567 #define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_SHIFT 17 568 #define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK 0x40000u 569 #define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT 18 570 #define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK 0x180000u 571 #define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT 19 572 #define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK) 573 #define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_MASK 0x200000u 574 #define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_SHIFT 21 575 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK 0xC00000u 576 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT 22 577 #define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK) 578 #define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_MASK 0x1000000u 579 #define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_SHIFT 24 580 #define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK 0x7E000000u 581 #define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT 25 582 #define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK) 583 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK 0x80000000u 584 #define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT 31 585 /* PLL_AUDIO_TOG Bit Fields */ 586 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK 0x7Fu 587 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT 0 588 #define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK) 589 #define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_MASK 0x80u 590 #define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_SHIFT 7 591 #define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_MASK 0x100u 592 #define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_SHIFT 8 593 #define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_MASK 0x200u 594 #define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_SHIFT 9 595 #define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_MASK 0x400u 596 #define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_SHIFT 10 597 #define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_MASK 0x800u 598 #define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_SHIFT 11 599 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK 0x1000u 600 #define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT 12 601 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_MASK 0x2000u 602 #define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_SHIFT 13 603 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK 0xC000u 604 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT 14 605 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK) 606 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK 0x10000u 607 #define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT 16 608 #define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_MASK 0x20000u 609 #define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_SHIFT 17 610 #define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK 0x40000u 611 #define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT 18 612 #define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK 0x180000u 613 #define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT 19 614 #define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK) 615 #define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_MASK 0x200000u 616 #define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_SHIFT 21 617 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK 0xC00000u 618 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT 22 619 #define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK) 620 #define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_MASK 0x1000000u 621 #define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_SHIFT 24 622 #define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK 0x7E000000u 623 #define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT 25 624 #define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK) 625 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK 0x80000000u 626 #define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT 31 627 /* PLL_AUDIO_SS Bit Fields */ 628 #define CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK 0x7FFFu 629 #define CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT 0 630 #define CCM_ANALOG_PLL_AUDIO_SS_STEP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK) 631 #define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_MASK 0x8000u 632 #define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_SHIFT 15 633 #define CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK 0xFFFF0000u 634 #define CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT 16 635 #define CCM_ANALOG_PLL_AUDIO_SS_STOP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK) 636 /* PLL_AUDIO_NUM Bit Fields */ 637 #define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK 0x3FFFFFFFu 638 #define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT 0 639 #define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_A_MASK) 640 #define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK 0xC0000000u 641 #define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT 30 642 #define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK) 643 /* PLL_AUDIO_DENOM Bit Fields */ 644 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK 0x3FFFFFFFu 645 #define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT 0 646 #define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK) 647 #define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK 0xC0000000u 648 #define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT 30 649 #define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK) 650 /* PLL_VIDEO Bit Fields */ 651 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK 0x7Fu 652 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT 0 653 #define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) 654 #define CCM_ANALOG_PLL_VIDEO_HALF_LF_MASK 0x80u 655 #define CCM_ANALOG_PLL_VIDEO_HALF_LF_SHIFT 7 656 #define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_MASK 0x100u 657 #define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_SHIFT 8 658 #define CCM_ANALOG_PLL_VIDEO_HALF_CP_MASK 0x200u 659 #define CCM_ANALOG_PLL_VIDEO_HALF_CP_SHIFT 9 660 #define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_MASK 0x400u 661 #define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_SHIFT 10 662 #define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_MASK 0x800u 663 #define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_SHIFT 11 664 #define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK 0x1000u 665 #define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT 12 666 #define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_MASK 0x2000u 667 #define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_SHIFT 13 668 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK 0xC000u 669 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT 14 670 #define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK) 671 #define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK 0x10000u 672 #define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT 16 673 #define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_MASK 0x20000u 674 #define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_SHIFT 17 675 #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK 0x40000u 676 #define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT 18 677 #define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK 0x180000u 678 #define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT 19 679 #define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK) 680 #define CCM_ANALOG_PLL_VIDEO_RSVD0_MASK 0x200000u 681 #define CCM_ANALOG_PLL_VIDEO_RSVD0_SHIFT 21 682 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK 0xC00000u 683 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT 22 684 #define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK) 685 #define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_MASK 0x1000000u 686 #define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_SHIFT 24 687 #define CCM_ANALOG_PLL_VIDEO_RSVD1_MASK 0x7E000000u 688 #define CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT 25 689 #define CCM_ANALOG_PLL_VIDEO_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_RSVD1_MASK) 690 #define CCM_ANALOG_PLL_VIDEO_LOCK_MASK 0x80000000u 691 #define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT 31 692 /* PLL_VIDEO_SET Bit Fields */ 693 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK 0x7Fu 694 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT 0 695 #define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK) 696 #define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_MASK 0x80u 697 #define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_SHIFT 7 698 #define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_MASK 0x100u 699 #define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_SHIFT 8 700 #define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_MASK 0x200u 701 #define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_SHIFT 9 702 #define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_MASK 0x400u 703 #define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_SHIFT 10 704 #define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_MASK 0x800u 705 #define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_SHIFT 11 706 #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK 0x1000u 707 #define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT 12 708 #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_MASK 0x2000u 709 #define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_SHIFT 13 710 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK 0xC000u 711 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT 14 712 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK) 713 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK 0x10000u 714 #define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT 16 715 #define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_MASK 0x20000u 716 #define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_SHIFT 17 717 #define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK 0x40000u 718 #define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT 18 719 #define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK 0x180000u 720 #define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT 19 721 #define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK) 722 #define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_MASK 0x200000u 723 #define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_SHIFT 21 724 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK 0xC00000u 725 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT 22 726 #define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK) 727 #define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_MASK 0x1000000u 728 #define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_SHIFT 24 729 #define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK 0x7E000000u 730 #define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT 25 731 #define CCM_ANALOG_PLL_VIDEO_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK) 732 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK 0x80000000u 733 #define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT 31 734 /* PLL_VIDEO_CLR Bit Fields */ 735 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK 0x7Fu 736 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT 0 737 #define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK) 738 #define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_MASK 0x80u 739 #define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_SHIFT 7 740 #define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_MASK 0x100u 741 #define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_SHIFT 8 742 #define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_MASK 0x200u 743 #define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_SHIFT 9 744 #define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_MASK 0x400u 745 #define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_SHIFT 10 746 #define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_MASK 0x800u 747 #define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_SHIFT 11 748 #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK 0x1000u 749 #define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT 12 750 #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK 0x2000u 751 #define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_SHIFT 13 752 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK 0xC000u 753 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT 14 754 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK) 755 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK 0x10000u 756 #define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT 16 757 #define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_MASK 0x20000u 758 #define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_SHIFT 17 759 #define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK 0x40000u 760 #define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT 18 761 #define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK 0x180000u 762 #define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT 19 763 #define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK) 764 #define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_MASK 0x200000u 765 #define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_SHIFT 21 766 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK 0xC00000u 767 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT 22 768 #define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK) 769 #define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_MASK 0x1000000u 770 #define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_SHIFT 24 771 #define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK 0x7E000000u 772 #define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT 25 773 #define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK) 774 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK 0x80000000u 775 #define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT 31 776 /* PLL_VIDEO_TOG Bit Fields */ 777 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK 0x7Fu 778 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT 0 779 #define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK) 780 #define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_MASK 0x80u 781 #define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_SHIFT 7 782 #define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_MASK 0x100u 783 #define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_SHIFT 8 784 #define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_MASK 0x200u 785 #define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_SHIFT 9 786 #define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_MASK 0x400u 787 #define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_SHIFT 10 788 #define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_MASK 0x800u 789 #define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_SHIFT 11 790 #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK 0x1000u 791 #define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT 12 792 #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_MASK 0x2000u 793 #define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_SHIFT 13 794 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK 0xC000u 795 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT 14 796 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK) 797 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK 0x10000u 798 #define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT 16 799 #define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_MASK 0x20000u 800 #define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_SHIFT 17 801 #define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK 0x40000u 802 #define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT 18 803 #define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK 0x180000u 804 #define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT 19 805 #define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK) 806 #define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_MASK 0x200000u 807 #define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_SHIFT 21 808 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK 0xC00000u 809 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT 22 810 #define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK) 811 #define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_MASK 0x1000000u 812 #define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_SHIFT 24 813 #define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK 0x7E000000u 814 #define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT 25 815 #define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK) 816 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK 0x80000000u 817 #define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT 31 818 /* PLL_VIDEO_SS Bit Fields */ 819 #define CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK 0x7FFFu 820 #define CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT 0 821 #define CCM_ANALOG_PLL_VIDEO_SS_STEP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK) 822 #define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_MASK 0x8000u 823 #define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_SHIFT 15 824 #define CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK 0xFFFF0000u 825 #define CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT 16 826 #define CCM_ANALOG_PLL_VIDEO_SS_STOP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK) 827 /* PLL_VIDEO_NUM Bit Fields */ 828 #define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK 0x3FFFFFFFu 829 #define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT 0 830 #define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_A_MASK) 831 #define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK 0xC0000000u 832 #define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT 30 833 #define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK) 834 /* PLL_VIDEO_DENOM Bit Fields */ 835 #define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK 0x3FFFFFFFu 836 #define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT 0 837 #define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK) 838 #define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK 0xC0000000u 839 #define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT 30 840 #define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK) 841 /* CLK_MISC0 Bit Fields */ 842 #define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK 0x1Fu 843 #define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT 0 844 #define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK) 845 #define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_MASK 0x20u 846 #define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_SHIFT 5 847 #define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_MASK 0x40u 848 #define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_SHIFT 6 849 #define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_MASK 0x80u 850 #define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_SHIFT 7 851 #define CCM_ANALOG_CLK_MISC0_RSVD0_MASK 0xFFFFFF00u 852 #define CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT 8 853 #define CCM_ANALOG_CLK_MISC0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_RSVD0_MASK) 854 /* CLK_MISC0_SET Bit Fields */ 855 #define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK 0x1Fu 856 #define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT 0 857 #define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK) 858 #define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_MASK 0x20u 859 #define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_SHIFT 5 860 #define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_MASK 0x40u 861 #define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_SHIFT 6 862 #define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_MASK 0x80u 863 #define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_SHIFT 7 864 #define CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK 0xFFFFFF00u 865 #define CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT 8 866 #define CCM_ANALOG_CLK_MISC0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK) 867 /* CLK_MISC0_CLR Bit Fields */ 868 #define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK 0x1Fu 869 #define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT 0 870 #define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK) 871 #define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_MASK 0x20u 872 #define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_SHIFT 5 873 #define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_MASK 0x40u 874 #define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_SHIFT 6 875 #define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_MASK 0x80u 876 #define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_SHIFT 7 877 #define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK 0xFFFFFF00u 878 #define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT 8 879 #define CCM_ANALOG_CLK_MISC0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK) 880 /* CLK_MISC0_TOG Bit Fields */ 881 #define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK 0x1Fu 882 #define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT 0 883 #define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK) 884 #define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_MASK 0x20u 885 #define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_SHIFT 5 886 #define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_MASK 0x40u 887 #define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_SHIFT 6 888 #define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_MASK 0x80u 889 #define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_SHIFT 7 890 #define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK 0xFFFFFF00u 891 #define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT 8 892 #define CCM_ANALOG_CLK_MISC0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK) 893 894 /* REG_1P0A Bit Fields */ 895 #define PMU_REG_1P0A_ENABLE_LINREG_MASK 0x1u 896 #define PMU_REG_1P0A_ENABLE_LINREG_SHIFT 0 897 #define PMU_REG_1P0A_ENABLE_BO_MASK 0x2u 898 #define PMU_REG_1P0A_ENABLE_BO_SHIFT 1 899 #define PMU_REG_1P0A_ENABLE_ILIMIT_MASK 0x4u 900 #define PMU_REG_1P0A_ENABLE_ILIMIT_SHIFT 2 901 #define PMU_REG_1P0A_ENABLE_PULLDOWN_MASK 0x8u 902 #define PMU_REG_1P0A_ENABLE_PULLDOWN_SHIFT 3 903 #define PMU_REG_1P0A_BO_OFFSET_MASK 0x70u 904 #define PMU_REG_1P0A_BO_OFFSET_SHIFT 4 905 #define PMU_REG_1P0A_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_BO_OFFSET_SHIFT))&PMU_REG_1P0A_BO_OFFSET_MASK) 906 #define PMU_REG_1P0A_ENABLE_PWRUPLOAD_MASK 0x80u 907 #define PMU_REG_1P0A_ENABLE_PWRUPLOAD_SHIFT 7 908 #define PMU_REG_1P0A_OUTPUT_TRG_MASK 0x1F00u 909 #define PMU_REG_1P0A_OUTPUT_TRG_SHIFT 8 910 #define PMU_REG_1P0A_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_OUTPUT_TRG_MASK) 911 #define PMU_REG_1P0A_RSVD0_MASK 0xE000u 912 #define PMU_REG_1P0A_RSVD0_SHIFT 13 913 #define PMU_REG_1P0A_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD0_SHIFT))&PMU_REG_1P0A_RSVD0_MASK) 914 #define PMU_REG_1P0A_BO_MASK 0x10000u 915 #define PMU_REG_1P0A_BO_SHIFT 16 916 #define PMU_REG_1P0A_OK_MASK 0x20000u 917 #define PMU_REG_1P0A_OK_SHIFT 17 918 #define PMU_REG_1P0A_ENABLE_WEAK_LINREG_MASK 0x40000u 919 #define PMU_REG_1P0A_ENABLE_WEAK_LINREG_SHIFT 18 920 #define PMU_REG_1P0A_SELREF_WEAK_LINREG_MASK 0x80000u 921 #define PMU_REG_1P0A_SELREF_WEAK_LINREG_SHIFT 19 922 #define PMU_REG_1P0A_REG_TEST_MASK 0xF00000u 923 #define PMU_REG_1P0A_REG_TEST_SHIFT 20 924 #define PMU_REG_1P0A_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_REG_TEST_SHIFT))&PMU_REG_1P0A_REG_TEST_MASK) 925 #define PMU_REG_1P0A_RSVD1_MASK 0xFF000000u 926 #define PMU_REG_1P0A_RSVD1_SHIFT 24 927 #define PMU_REG_1P0A_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD1_SHIFT))&PMU_REG_1P0A_RSVD1_MASK) 928 /* REG_1P0A_SET Bit Fields */ 929 #define PMU_REG_1P0A_SET_ENABLE_LINREG_MASK 0x1u 930 #define PMU_REG_1P0A_SET_ENABLE_LINREG_SHIFT 0 931 #define PMU_REG_1P0A_SET_ENABLE_BO_MASK 0x2u 932 #define PMU_REG_1P0A_SET_ENABLE_BO_SHIFT 1 933 #define PMU_REG_1P0A_SET_ENABLE_ILIMIT_MASK 0x4u 934 #define PMU_REG_1P0A_SET_ENABLE_ILIMIT_SHIFT 2 935 #define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_MASK 0x8u 936 #define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_SHIFT 3 937 #define PMU_REG_1P0A_SET_BO_OFFSET_MASK 0x70u 938 #define PMU_REG_1P0A_SET_BO_OFFSET_SHIFT 4 939 #define PMU_REG_1P0A_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0A_SET_BO_OFFSET_MASK) 940 #define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_MASK 0x80u 941 #define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_SHIFT 7 942 #define PMU_REG_1P0A_SET_OUTPUT_TRG_MASK 0x1F00u 943 #define PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT 8 944 #define PMU_REG_1P0A_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_SET_OUTPUT_TRG_MASK) 945 #define PMU_REG_1P0A_SET_RSVD0_MASK 0xE000u 946 #define PMU_REG_1P0A_SET_RSVD0_SHIFT 13 947 #define PMU_REG_1P0A_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD0_SHIFT))&PMU_REG_1P0A_SET_RSVD0_MASK) 948 #define PMU_REG_1P0A_SET_BO_MASK 0x10000u 949 #define PMU_REG_1P0A_SET_BO_SHIFT 16 950 #define PMU_REG_1P0A_SET_OK_MASK 0x20000u 951 #define PMU_REG_1P0A_SET_OK_SHIFT 17 952 #define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_MASK 0x40000u 953 #define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_SHIFT 18 954 #define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_MASK 0x80000u 955 #define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_SHIFT 19 956 #define PMU_REG_1P0A_SET_REG_TEST_MASK 0xF00000u 957 #define PMU_REG_1P0A_SET_REG_TEST_SHIFT 20 958 #define PMU_REG_1P0A_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_REG_TEST_SHIFT))&PMU_REG_1P0A_SET_REG_TEST_MASK) 959 #define PMU_REG_1P0A_SET_RSVD1_MASK 0xFF000000u 960 #define PMU_REG_1P0A_SET_RSVD1_SHIFT 24 961 #define PMU_REG_1P0A_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD1_SHIFT))&PMU_REG_1P0A_SET_RSVD1_MASK) 962 /* REG_1P0A_CLR Bit Fields */ 963 #define PMU_REG_1P0A_CLR_ENABLE_LINREG_MASK 0x1u 964 #define PMU_REG_1P0A_CLR_ENABLE_LINREG_SHIFT 0 965 #define PMU_REG_1P0A_CLR_ENABLE_BO_MASK 0x2u 966 #define PMU_REG_1P0A_CLR_ENABLE_BO_SHIFT 1 967 #define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_MASK 0x4u 968 #define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_SHIFT 2 969 #define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_MASK 0x8u 970 #define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_SHIFT 3 971 #define PMU_REG_1P0A_CLR_BO_OFFSET_MASK 0x70u 972 #define PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT 4 973 #define PMU_REG_1P0A_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0A_CLR_BO_OFFSET_MASK) 974 #define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_MASK 0x80u 975 #define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_SHIFT 7 976 #define PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK 0x1F00u 977 #define PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT 8 978 #define PMU_REG_1P0A_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK) 979 #define PMU_REG_1P0A_CLR_RSVD0_MASK 0xE000u 980 #define PMU_REG_1P0A_CLR_RSVD0_SHIFT 13 981 #define PMU_REG_1P0A_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD0_SHIFT))&PMU_REG_1P0A_CLR_RSVD0_MASK) 982 #define PMU_REG_1P0A_CLR_BO_MASK 0x10000u 983 #define PMU_REG_1P0A_CLR_BO_SHIFT 16 984 #define PMU_REG_1P0A_CLR_OK_MASK 0x20000u 985 #define PMU_REG_1P0A_CLR_OK_SHIFT 17 986 #define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u 987 #define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_SHIFT 18 988 #define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_MASK 0x80000u 989 #define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_SHIFT 19 990 #define PMU_REG_1P0A_CLR_REG_TEST_MASK 0xF00000u 991 #define PMU_REG_1P0A_CLR_REG_TEST_SHIFT 20 992 #define PMU_REG_1P0A_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_REG_TEST_SHIFT))&PMU_REG_1P0A_CLR_REG_TEST_MASK) 993 #define PMU_REG_1P0A_CLR_RSVD1_MASK 0xFF000000u 994 #define PMU_REG_1P0A_CLR_RSVD1_SHIFT 24 995 #define PMU_REG_1P0A_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD1_SHIFT))&PMU_REG_1P0A_CLR_RSVD1_MASK) 996 /* REG_1P0A_TOG Bit Fields */ 997 #define PMU_REG_1P0A_TOG_ENABLE_LINREG_MASK 0x1u 998 #define PMU_REG_1P0A_TOG_ENABLE_LINREG_SHIFT 0 999 #define PMU_REG_1P0A_TOG_ENABLE_BO_MASK 0x2u 1000 #define PMU_REG_1P0A_TOG_ENABLE_BO_SHIFT 1 1001 #define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_MASK 0x4u 1002 #define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_SHIFT 2 1003 #define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_MASK 0x8u 1004 #define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_SHIFT 3 1005 #define PMU_REG_1P0A_TOG_BO_OFFSET_MASK 0x70u 1006 #define PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT 4 1007 #define PMU_REG_1P0A_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0A_TOG_BO_OFFSET_MASK) 1008 #define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_MASK 0x80u 1009 #define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_SHIFT 7 1010 #define PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK 0x1F00u 1011 #define PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT 8 1012 #define PMU_REG_1P0A_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK) 1013 #define PMU_REG_1P0A_TOG_RSVD0_MASK 0xE000u 1014 #define PMU_REG_1P0A_TOG_RSVD0_SHIFT 13 1015 #define PMU_REG_1P0A_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD0_SHIFT))&PMU_REG_1P0A_TOG_RSVD0_MASK) 1016 #define PMU_REG_1P0A_TOG_BO_MASK 0x10000u 1017 #define PMU_REG_1P0A_TOG_BO_SHIFT 16 1018 #define PMU_REG_1P0A_TOG_OK_MASK 0x20000u 1019 #define PMU_REG_1P0A_TOG_OK_SHIFT 17 1020 #define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u 1021 #define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_SHIFT 18 1022 #define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_MASK 0x80000u 1023 #define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_SHIFT 19 1024 #define PMU_REG_1P0A_TOG_REG_TEST_MASK 0xF00000u 1025 #define PMU_REG_1P0A_TOG_REG_TEST_SHIFT 20 1026 #define PMU_REG_1P0A_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_REG_TEST_SHIFT))&PMU_REG_1P0A_TOG_REG_TEST_MASK) 1027 #define PMU_REG_1P0A_TOG_RSVD1_MASK 0xFF000000u 1028 #define PMU_REG_1P0A_TOG_RSVD1_SHIFT 24 1029 #define PMU_REG_1P0A_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD1_SHIFT))&PMU_REG_1P0A_TOG_RSVD1_MASK) 1030 /* REG_1P0D Bit Fields */ 1031 #define PMU_REG_1P0D_ENABLE_LINREG_MASK 0x1u 1032 #define PMU_REG_1P0D_ENABLE_LINREG_SHIFT 0 1033 #define PMU_REG_1P0D_ENABLE_BO_MASK 0x2u 1034 #define PMU_REG_1P0D_ENABLE_BO_SHIFT 1 1035 #define PMU_REG_1P0D_ENABLE_ILIMIT_MASK 0x4u 1036 #define PMU_REG_1P0D_ENABLE_ILIMIT_SHIFT 2 1037 #define PMU_REG_1P0D_ENABLE_PULLDOWN_MASK 0x8u 1038 #define PMU_REG_1P0D_ENABLE_PULLDOWN_SHIFT 3 1039 #define PMU_REG_1P0D_BO_OFFSET_MASK 0x70u 1040 #define PMU_REG_1P0D_BO_OFFSET_SHIFT 4 1041 #define PMU_REG_1P0D_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_BO_OFFSET_SHIFT))&PMU_REG_1P0D_BO_OFFSET_MASK) 1042 #define PMU_REG_1P0D_ENABLE_PWRUPLOAD_MASK 0x80u 1043 #define PMU_REG_1P0D_ENABLE_PWRUPLOAD_SHIFT 7 1044 #define PMU_REG_1P0D_OUTPUT_TRG_MASK 0x1F00u 1045 #define PMU_REG_1P0D_OUTPUT_TRG_SHIFT 8 1046 #define PMU_REG_1P0D_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_OUTPUT_TRG_MASK) 1047 #define PMU_REG_1P0D_RSVD0_MASK 0xE000u 1048 #define PMU_REG_1P0D_RSVD0_SHIFT 13 1049 #define PMU_REG_1P0D_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD0_SHIFT))&PMU_REG_1P0D_RSVD0_MASK) 1050 #define PMU_REG_1P0D_BO_MASK 0x10000u 1051 #define PMU_REG_1P0D_BO_SHIFT 16 1052 #define PMU_REG_1P0D_OK_MASK 0x20000u 1053 #define PMU_REG_1P0D_OK_SHIFT 17 1054 #define PMU_REG_1P0D_ENABLE_WEAK_LINREG_MASK 0x40000u 1055 #define PMU_REG_1P0D_ENABLE_WEAK_LINREG_SHIFT 18 1056 #define PMU_REG_1P0D_SELREF_WEAK_LINREG_MASK 0x80000u 1057 #define PMU_REG_1P0D_SELREF_WEAK_LINREG_SHIFT 19 1058 #define PMU_REG_1P0D_REG_TEST_MASK 0xF00000u 1059 #define PMU_REG_1P0D_REG_TEST_SHIFT 20 1060 #define PMU_REG_1P0D_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_REG_TEST_SHIFT))&PMU_REG_1P0D_REG_TEST_MASK) 1061 #define PMU_REG_1P0D_RSVD1_MASK 0x7F000000u 1062 #define PMU_REG_1P0D_RSVD1_SHIFT 24 1063 #define PMU_REG_1P0D_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD1_SHIFT))&PMU_REG_1P0D_RSVD1_MASK) 1064 #define PMU_REG_1P0D_OVERRIDE_MASK 0x80000000u 1065 #define PMU_REG_1P0D_OVERRIDE_SHIFT 31 1066 /* REG_1P0D_SET Bit Fields */ 1067 #define PMU_REG_1P0D_SET_ENABLE_LINREG_MASK 0x1u 1068 #define PMU_REG_1P0D_SET_ENABLE_LINREG_SHIFT 0 1069 #define PMU_REG_1P0D_SET_ENABLE_BO_MASK 0x2u 1070 #define PMU_REG_1P0D_SET_ENABLE_BO_SHIFT 1 1071 #define PMU_REG_1P0D_SET_ENABLE_ILIMIT_MASK 0x4u 1072 #define PMU_REG_1P0D_SET_ENABLE_ILIMIT_SHIFT 2 1073 #define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_MASK 0x8u 1074 #define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_SHIFT 3 1075 #define PMU_REG_1P0D_SET_BO_OFFSET_MASK 0x70u 1076 #define PMU_REG_1P0D_SET_BO_OFFSET_SHIFT 4 1077 #define PMU_REG_1P0D_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0D_SET_BO_OFFSET_MASK) 1078 #define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_MASK 0x80u 1079 #define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_SHIFT 7 1080 #define PMU_REG_1P0D_SET_OUTPUT_TRG_MASK 0x1F00u 1081 #define PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT 8 1082 #define PMU_REG_1P0D_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_SET_OUTPUT_TRG_MASK) 1083 #define PMU_REG_1P0D_SET_RSVD0_MASK 0xE000u 1084 #define PMU_REG_1P0D_SET_RSVD0_SHIFT 13 1085 #define PMU_REG_1P0D_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD0_SHIFT))&PMU_REG_1P0D_SET_RSVD0_MASK) 1086 #define PMU_REG_1P0D_SET_BO_MASK 0x10000u 1087 #define PMU_REG_1P0D_SET_BO_SHIFT 16 1088 #define PMU_REG_1P0D_SET_OK_MASK 0x20000u 1089 #define PMU_REG_1P0D_SET_OK_SHIFT 17 1090 #define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_MASK 0x40000u 1091 #define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_SHIFT 18 1092 #define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_MASK 0x80000u 1093 #define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_SHIFT 19 1094 #define PMU_REG_1P0D_SET_REG_TEST_MASK 0xF00000u 1095 #define PMU_REG_1P0D_SET_REG_TEST_SHIFT 20 1096 #define PMU_REG_1P0D_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_REG_TEST_SHIFT))&PMU_REG_1P0D_SET_REG_TEST_MASK) 1097 #define PMU_REG_1P0D_SET_RSVD1_MASK 0x7F000000u 1098 #define PMU_REG_1P0D_SET_RSVD1_SHIFT 24 1099 #define PMU_REG_1P0D_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD1_SHIFT))&PMU_REG_1P0D_SET_RSVD1_MASK) 1100 #define PMU_REG_1P0D_SET_OVERRIDE_MASK 0x80000000u 1101 #define PMU_REG_1P0D_SET_OVERRIDE_SHIFT 31 1102 /* REG_1P0D_CLR Bit Fields */ 1103 #define PMU_REG_1P0D_CLR_ENABLE_LINREG_MASK 0x1u 1104 #define PMU_REG_1P0D_CLR_ENABLE_LINREG_SHIFT 0 1105 #define PMU_REG_1P0D_CLR_ENABLE_BO_MASK 0x2u 1106 #define PMU_REG_1P0D_CLR_ENABLE_BO_SHIFT 1 1107 #define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_MASK 0x4u 1108 #define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_SHIFT 2 1109 #define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_MASK 0x8u 1110 #define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_SHIFT 3 1111 #define PMU_REG_1P0D_CLR_BO_OFFSET_MASK 0x70u 1112 #define PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT 4 1113 #define PMU_REG_1P0D_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0D_CLR_BO_OFFSET_MASK) 1114 #define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_MASK 0x80u 1115 #define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_SHIFT 7 1116 #define PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK 0x1F00u 1117 #define PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT 8 1118 #define PMU_REG_1P0D_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK) 1119 #define PMU_REG_1P0D_CLR_RSVD0_MASK 0xE000u 1120 #define PMU_REG_1P0D_CLR_RSVD0_SHIFT 13 1121 #define PMU_REG_1P0D_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD0_SHIFT))&PMU_REG_1P0D_CLR_RSVD0_MASK) 1122 #define PMU_REG_1P0D_CLR_BO_MASK 0x10000u 1123 #define PMU_REG_1P0D_CLR_BO_SHIFT 16 1124 #define PMU_REG_1P0D_CLR_OK_MASK 0x20000u 1125 #define PMU_REG_1P0D_CLR_OK_SHIFT 17 1126 #define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u 1127 #define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_SHIFT 18 1128 #define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_MASK 0x80000u 1129 #define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_SHIFT 19 1130 #define PMU_REG_1P0D_CLR_REG_TEST_MASK 0xF00000u 1131 #define PMU_REG_1P0D_CLR_REG_TEST_SHIFT 20 1132 #define PMU_REG_1P0D_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_REG_TEST_SHIFT))&PMU_REG_1P0D_CLR_REG_TEST_MASK) 1133 #define PMU_REG_1P0D_CLR_RSVD1_MASK 0x7F000000u 1134 #define PMU_REG_1P0D_CLR_RSVD1_SHIFT 24 1135 #define PMU_REG_1P0D_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD1_SHIFT))&PMU_REG_1P0D_CLR_RSVD1_MASK) 1136 #define PMU_REG_1P0D_CLR_OVERRIDE_MASK 0x80000000u 1137 #define PMU_REG_1P0D_CLR_OVERRIDE_SHIFT 31 1138 /* REG_1P0D_TOG Bit Fields */ 1139 #define PMU_REG_1P0D_TOG_ENABLE_LINREG_MASK 0x1u 1140 #define PMU_REG_1P0D_TOG_ENABLE_LINREG_SHIFT 0 1141 #define PMU_REG_1P0D_TOG_ENABLE_BO_MASK 0x2u 1142 #define PMU_REG_1P0D_TOG_ENABLE_BO_SHIFT 1 1143 #define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_MASK 0x4u 1144 #define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_SHIFT 2 1145 #define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_MASK 0x8u 1146 #define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_SHIFT 3 1147 #define PMU_REG_1P0D_TOG_BO_OFFSET_MASK 0x70u 1148 #define PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT 4 1149 #define PMU_REG_1P0D_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0D_TOG_BO_OFFSET_MASK) 1150 #define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_MASK 0x80u 1151 #define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_SHIFT 7 1152 #define PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK 0x1F00u 1153 #define PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT 8 1154 #define PMU_REG_1P0D_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK) 1155 #define PMU_REG_1P0D_TOG_RSVD0_MASK 0xE000u 1156 #define PMU_REG_1P0D_TOG_RSVD0_SHIFT 13 1157 #define PMU_REG_1P0D_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD0_SHIFT))&PMU_REG_1P0D_TOG_RSVD0_MASK) 1158 #define PMU_REG_1P0D_TOG_BO_MASK 0x10000u 1159 #define PMU_REG_1P0D_TOG_BO_SHIFT 16 1160 #define PMU_REG_1P0D_TOG_OK_MASK 0x20000u 1161 #define PMU_REG_1P0D_TOG_OK_SHIFT 17 1162 #define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u 1163 #define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_SHIFT 18 1164 #define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_MASK 0x80000u 1165 #define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_SHIFT 19 1166 #define PMU_REG_1P0D_TOG_REG_TEST_MASK 0xF00000u 1167 #define PMU_REG_1P0D_TOG_REG_TEST_SHIFT 20 1168 #define PMU_REG_1P0D_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_REG_TEST_SHIFT))&PMU_REG_1P0D_TOG_REG_TEST_MASK) 1169 #define PMU_REG_1P0D_TOG_RSVD1_MASK 0x7F000000u 1170 #define PMU_REG_1P0D_TOG_RSVD1_SHIFT 24 1171 #define PMU_REG_1P0D_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD1_SHIFT))&PMU_REG_1P0D_TOG_RSVD1_MASK) 1172 #define PMU_REG_1P0D_TOG_OVERRIDE_MASK 0x80000000u 1173 #define PMU_REG_1P0D_TOG_OVERRIDE_SHIFT 31 1174 /* REG_HSIC_1P2 Bit Fields */ 1175 #define PMU_REG_HSIC_1P2_ENABLE_LINREG_MASK 0x1u 1176 #define PMU_REG_HSIC_1P2_ENABLE_LINREG_SHIFT 0 1177 #define PMU_REG_HSIC_1P2_ENABLE_BO_MASK 0x2u 1178 #define PMU_REG_HSIC_1P2_ENABLE_BO_SHIFT 1 1179 #define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_MASK 0x4u 1180 #define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_SHIFT 2 1181 #define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_MASK 0x8u 1182 #define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_SHIFT 3 1183 #define PMU_REG_HSIC_1P2_BO_OFFSET_MASK 0x70u 1184 #define PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT 4 1185 #define PMU_REG_HSIC_1P2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_BO_OFFSET_MASK) 1186 #define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_MASK 0x80u 1187 #define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_SHIFT 7 1188 #define PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK 0x1F00u 1189 #define PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT 8 1190 #define PMU_REG_HSIC_1P2_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK) 1191 #define PMU_REG_HSIC_1P2_RSVD0_MASK 0xE000u 1192 #define PMU_REG_HSIC_1P2_RSVD0_SHIFT 13 1193 #define PMU_REG_HSIC_1P2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_RSVD0_MASK) 1194 #define PMU_REG_HSIC_1P2_BO_MASK 0x10000u 1195 #define PMU_REG_HSIC_1P2_BO_SHIFT 16 1196 #define PMU_REG_HSIC_1P2_OK_MASK 0x20000u 1197 #define PMU_REG_HSIC_1P2_OK_SHIFT 17 1198 #define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_MASK 0x40000u 1199 #define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_SHIFT 18 1200 #define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_MASK 0x80000u 1201 #define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_SHIFT 19 1202 #define PMU_REG_HSIC_1P2_REG_TEST_MASK 0xF00000u 1203 #define PMU_REG_HSIC_1P2_REG_TEST_SHIFT 20 1204 #define PMU_REG_HSIC_1P2_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_REG_TEST_MASK) 1205 #define PMU_REG_HSIC_1P2_RSVD1_MASK 0x7F000000u 1206 #define PMU_REG_HSIC_1P2_RSVD1_SHIFT 24 1207 #define PMU_REG_HSIC_1P2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_RSVD1_MASK) 1208 #define PMU_REG_HSIC_1P2_OVERRIDE_MASK 0x80000000u 1209 #define PMU_REG_HSIC_1P2_OVERRIDE_SHIFT 31 1210 /* REG_HSIC_1P2_SET Bit Fields */ 1211 #define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_MASK 0x1u 1212 #define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_SHIFT 0 1213 #define PMU_REG_HSIC_1P2_SET_ENABLE_BO_MASK 0x2u 1214 #define PMU_REG_HSIC_1P2_SET_ENABLE_BO_SHIFT 1 1215 #define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_MASK 0x4u 1216 #define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_SHIFT 2 1217 #define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_MASK 0x8u 1218 #define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_SHIFT 3 1219 #define PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK 0x70u 1220 #define PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT 4 1221 #define PMU_REG_HSIC_1P2_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK) 1222 #define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_MASK 0x80u 1223 #define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_SHIFT 7 1224 #define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK 0x1F00u 1225 #define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT 8 1226 #define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK) 1227 #define PMU_REG_HSIC_1P2_SET_RSVD0_MASK 0xE000u 1228 #define PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT 13 1229 #define PMU_REG_HSIC_1P2_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD0_MASK) 1230 #define PMU_REG_HSIC_1P2_SET_BO_MASK 0x10000u 1231 #define PMU_REG_HSIC_1P2_SET_BO_SHIFT 16 1232 #define PMU_REG_HSIC_1P2_SET_OK_MASK 0x20000u 1233 #define PMU_REG_HSIC_1P2_SET_OK_SHIFT 17 1234 #define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_MASK 0x40000u 1235 #define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_SHIFT 18 1236 #define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_MASK 0x80000u 1237 #define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_SHIFT 19 1238 #define PMU_REG_HSIC_1P2_SET_REG_TEST_MASK 0xF00000u 1239 #define PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT 20 1240 #define PMU_REG_HSIC_1P2_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_SET_REG_TEST_MASK) 1241 #define PMU_REG_HSIC_1P2_SET_RSVD1_MASK 0x7F000000u 1242 #define PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT 24 1243 #define PMU_REG_HSIC_1P2_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD1_MASK) 1244 #define PMU_REG_HSIC_1P2_SET_OVERRIDE_MASK 0x80000000u 1245 #define PMU_REG_HSIC_1P2_SET_OVERRIDE_SHIFT 31 1246 /* REG_HSIC_1P2_CLR Bit Fields */ 1247 #define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_MASK 0x1u 1248 #define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_SHIFT 0 1249 #define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_MASK 0x2u 1250 #define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_SHIFT 1 1251 #define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_MASK 0x4u 1252 #define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_SHIFT 2 1253 #define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_MASK 0x8u 1254 #define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_SHIFT 3 1255 #define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK 0x70u 1256 #define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT 4 1257 #define PMU_REG_HSIC_1P2_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK) 1258 #define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_MASK 0x80u 1259 #define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_SHIFT 7 1260 #define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK 0x1F00u 1261 #define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT 8 1262 #define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK) 1263 #define PMU_REG_HSIC_1P2_CLR_RSVD0_MASK 0xE000u 1264 #define PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT 13 1265 #define PMU_REG_HSIC_1P2_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD0_MASK) 1266 #define PMU_REG_HSIC_1P2_CLR_BO_MASK 0x10000u 1267 #define PMU_REG_HSIC_1P2_CLR_BO_SHIFT 16 1268 #define PMU_REG_HSIC_1P2_CLR_OK_MASK 0x20000u 1269 #define PMU_REG_HSIC_1P2_CLR_OK_SHIFT 17 1270 #define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u 1271 #define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_SHIFT 18 1272 #define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_MASK 0x80000u 1273 #define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_SHIFT 19 1274 #define PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK 0xF00000u 1275 #define PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT 20 1276 #define PMU_REG_HSIC_1P2_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK) 1277 #define PMU_REG_HSIC_1P2_CLR_RSVD1_MASK 0x7F000000u 1278 #define PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT 24 1279 #define PMU_REG_HSIC_1P2_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD1_MASK) 1280 #define PMU_REG_HSIC_1P2_CLR_OVERRIDE_MASK 0x80000000u 1281 #define PMU_REG_HSIC_1P2_CLR_OVERRIDE_SHIFT 31 1282 /* REG_HSIC_1P2_TOG Bit Fields */ 1283 #define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_MASK 0x1u 1284 #define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_SHIFT 0 1285 #define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_MASK 0x2u 1286 #define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_SHIFT 1 1287 #define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_MASK 0x4u 1288 #define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_SHIFT 2 1289 #define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_MASK 0x8u 1290 #define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_SHIFT 3 1291 #define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK 0x70u 1292 #define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT 4 1293 #define PMU_REG_HSIC_1P2_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK) 1294 #define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_MASK 0x80u 1295 #define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_SHIFT 7 1296 #define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK 0x1F00u 1297 #define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT 8 1298 #define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK) 1299 #define PMU_REG_HSIC_1P2_TOG_RSVD0_MASK 0xE000u 1300 #define PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT 13 1301 #define PMU_REG_HSIC_1P2_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD0_MASK) 1302 #define PMU_REG_HSIC_1P2_TOG_BO_MASK 0x10000u 1303 #define PMU_REG_HSIC_1P2_TOG_BO_SHIFT 16 1304 #define PMU_REG_HSIC_1P2_TOG_OK_MASK 0x20000u 1305 #define PMU_REG_HSIC_1P2_TOG_OK_SHIFT 17 1306 #define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u 1307 #define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_SHIFT 18 1308 #define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_MASK 0x80000u 1309 #define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_SHIFT 19 1310 #define PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK 0xF00000u 1311 #define PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT 20 1312 #define PMU_REG_HSIC_1P2_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK) 1313 #define PMU_REG_HSIC_1P2_TOG_RSVD1_MASK 0x7F000000u 1314 #define PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT 24 1315 #define PMU_REG_HSIC_1P2_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD1_MASK) 1316 #define PMU_REG_HSIC_1P2_TOG_OVERRIDE_MASK 0x80000000u 1317 #define PMU_REG_HSIC_1P2_TOG_OVERRIDE_SHIFT 31 1318 /* REG_LPSR_1P0 Bit Fields */ 1319 #define PMU_REG_LPSR_1P0_ENABLE_LINREG_MASK 0x1u 1320 #define PMU_REG_LPSR_1P0_ENABLE_LINREG_SHIFT 0 1321 #define PMU_REG_LPSR_1P0_ENABLE_BO_MASK 0x2u 1322 #define PMU_REG_LPSR_1P0_ENABLE_BO_SHIFT 1 1323 #define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_MASK 0x4u 1324 #define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_SHIFT 2 1325 #define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_MASK 0x8u 1326 #define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_SHIFT 3 1327 #define PMU_REG_LPSR_1P0_BO_OFFSET_MASK 0x70u 1328 #define PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT 4 1329 #define PMU_REG_LPSR_1P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_BO_OFFSET_MASK) 1330 #define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_MASK 0x80u 1331 #define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_SHIFT 7 1332 #define PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK 0x1F00u 1333 #define PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT 8 1334 #define PMU_REG_LPSR_1P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK) 1335 #define PMU_REG_LPSR_1P0_RSVD0_MASK 0xE000u 1336 #define PMU_REG_LPSR_1P0_RSVD0_SHIFT 13 1337 #define PMU_REG_LPSR_1P0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_RSVD0_MASK) 1338 #define PMU_REG_LPSR_1P0_BO_MASK 0x10000u 1339 #define PMU_REG_LPSR_1P0_BO_SHIFT 16 1340 #define PMU_REG_LPSR_1P0_OK_MASK 0x20000u 1341 #define PMU_REG_LPSR_1P0_OK_SHIFT 17 1342 #define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_MASK 0x40000u 1343 #define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_SHIFT 18 1344 #define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_MASK 0x80000u 1345 #define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_SHIFT 19 1346 #define PMU_REG_LPSR_1P0_REG_TEST_MASK 0xF00000u 1347 #define PMU_REG_LPSR_1P0_REG_TEST_SHIFT 20 1348 #define PMU_REG_LPSR_1P0_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_REG_TEST_MASK) 1349 #define PMU_REG_LPSR_1P0_RSVD1_MASK 0xFF000000u 1350 #define PMU_REG_LPSR_1P0_RSVD1_SHIFT 24 1351 #define PMU_REG_LPSR_1P0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_RSVD1_MASK) 1352 /* REG_LPSR_1P0_SET Bit Fields */ 1353 #define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_MASK 0x1u 1354 #define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_SHIFT 0 1355 #define PMU_REG_LPSR_1P0_SET_ENABLE_BO_MASK 0x2u 1356 #define PMU_REG_LPSR_1P0_SET_ENABLE_BO_SHIFT 1 1357 #define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_MASK 0x4u 1358 #define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_SHIFT 2 1359 #define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_MASK 0x8u 1360 #define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_SHIFT 3 1361 #define PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK 0x70u 1362 #define PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT 4 1363 #define PMU_REG_LPSR_1P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK) 1364 #define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_MASK 0x80u 1365 #define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_SHIFT 7 1366 #define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK 0x1F00u 1367 #define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT 8 1368 #define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK) 1369 #define PMU_REG_LPSR_1P0_SET_RSVD0_MASK 0xE000u 1370 #define PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT 13 1371 #define PMU_REG_LPSR_1P0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD0_MASK) 1372 #define PMU_REG_LPSR_1P0_SET_BO_MASK 0x10000u 1373 #define PMU_REG_LPSR_1P0_SET_BO_SHIFT 16 1374 #define PMU_REG_LPSR_1P0_SET_OK_MASK 0x20000u 1375 #define PMU_REG_LPSR_1P0_SET_OK_SHIFT 17 1376 #define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_MASK 0x40000u 1377 #define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_SHIFT 18 1378 #define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_MASK 0x80000u 1379 #define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_SHIFT 19 1380 #define PMU_REG_LPSR_1P0_SET_REG_TEST_MASK 0xF00000u 1381 #define PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT 20 1382 #define PMU_REG_LPSR_1P0_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_SET_REG_TEST_MASK) 1383 #define PMU_REG_LPSR_1P0_SET_RSVD1_MASK 0xFF000000u 1384 #define PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT 24 1385 #define PMU_REG_LPSR_1P0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD1_MASK) 1386 /* REG_LPSR_1P0_CLR Bit Fields */ 1387 #define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_MASK 0x1u 1388 #define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_SHIFT 0 1389 #define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_MASK 0x2u 1390 #define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_SHIFT 1 1391 #define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_MASK 0x4u 1392 #define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_SHIFT 2 1393 #define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_MASK 0x8u 1394 #define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_SHIFT 3 1395 #define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK 0x70u 1396 #define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT 4 1397 #define PMU_REG_LPSR_1P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK) 1398 #define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_MASK 0x80u 1399 #define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_SHIFT 7 1400 #define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK 0x1F00u 1401 #define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT 8 1402 #define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK) 1403 #define PMU_REG_LPSR_1P0_CLR_RSVD0_MASK 0xE000u 1404 #define PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT 13 1405 #define PMU_REG_LPSR_1P0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD0_MASK) 1406 #define PMU_REG_LPSR_1P0_CLR_BO_MASK 0x10000u 1407 #define PMU_REG_LPSR_1P0_CLR_BO_SHIFT 16 1408 #define PMU_REG_LPSR_1P0_CLR_OK_MASK 0x20000u 1409 #define PMU_REG_LPSR_1P0_CLR_OK_SHIFT 17 1410 #define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u 1411 #define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_SHIFT 18 1412 #define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_MASK 0x80000u 1413 #define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_SHIFT 19 1414 #define PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK 0xF00000u 1415 #define PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT 20 1416 #define PMU_REG_LPSR_1P0_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK) 1417 #define PMU_REG_LPSR_1P0_CLR_RSVD1_MASK 0xFF000000u 1418 #define PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT 24 1419 #define PMU_REG_LPSR_1P0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD1_MASK) 1420 /* REG_LPSR_1P0_TOG Bit Fields */ 1421 #define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_MASK 0x1u 1422 #define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_SHIFT 0 1423 #define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_MASK 0x2u 1424 #define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_SHIFT 1 1425 #define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_MASK 0x4u 1426 #define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_SHIFT 2 1427 #define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_MASK 0x8u 1428 #define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_SHIFT 3 1429 #define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK 0x70u 1430 #define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT 4 1431 #define PMU_REG_LPSR_1P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK) 1432 #define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_MASK 0x80u 1433 #define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_SHIFT 7 1434 #define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK 0x1F00u 1435 #define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT 8 1436 #define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK) 1437 #define PMU_REG_LPSR_1P0_TOG_RSVD0_MASK 0xE000u 1438 #define PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT 13 1439 #define PMU_REG_LPSR_1P0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD0_MASK) 1440 #define PMU_REG_LPSR_1P0_TOG_BO_MASK 0x10000u 1441 #define PMU_REG_LPSR_1P0_TOG_BO_SHIFT 16 1442 #define PMU_REG_LPSR_1P0_TOG_OK_MASK 0x20000u 1443 #define PMU_REG_LPSR_1P0_TOG_OK_SHIFT 17 1444 #define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u 1445 #define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_SHIFT 18 1446 #define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_MASK 0x80000u 1447 #define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_SHIFT 19 1448 #define PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK 0xF00000u 1449 #define PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT 20 1450 #define PMU_REG_LPSR_1P0_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK) 1451 #define PMU_REG_LPSR_1P0_TOG_RSVD1_MASK 0xFF000000u 1452 #define PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT 24 1453 #define PMU_REG_LPSR_1P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD1_MASK) 1454 /* REG_3P0 Bit Fields */ 1455 #define PMU_REG_3P0_ENABLE_LINREG_MASK 0x1u 1456 #define PMU_REG_3P0_ENABLE_LINREG_SHIFT 0 1457 #define PMU_REG_3P0_ENABLE_BO_MASK 0x2u 1458 #define PMU_REG_3P0_ENABLE_BO_SHIFT 1 1459 #define PMU_REG_3P0_ENABLE_ILIMIT_MASK 0x4u 1460 #define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT 2 1461 #define PMU_REG_3P0_RSVD0_MASK 0x8u 1462 #define PMU_REG_3P0_RSVD0_SHIFT 3 1463 #define PMU_REG_3P0_BO_OFFSET_MASK 0x70u 1464 #define PMU_REG_3P0_BO_OFFSET_SHIFT 4 1465 #define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_BO_OFFSET_SHIFT))&PMU_REG_3P0_BO_OFFSET_MASK) 1466 #define PMU_REG_3P0_VBUS_SEL_MASK 0x80u 1467 #define PMU_REG_3P0_VBUS_SEL_SHIFT 7 1468 #define PMU_REG_3P0_OUTPUT_TRG_MASK 0x1F00u 1469 #define PMU_REG_3P0_OUTPUT_TRG_SHIFT 8 1470 #define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_OUTPUT_TRG_MASK) 1471 #define PMU_REG_3P0_RSVD1_MASK 0xE000u 1472 #define PMU_REG_3P0_RSVD1_SHIFT 13 1473 #define PMU_REG_3P0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD1_SHIFT))&PMU_REG_3P0_RSVD1_MASK) 1474 #define PMU_REG_3P0_BO_VDD3P0_MASK 0x10000u 1475 #define PMU_REG_3P0_BO_VDD3P0_SHIFT 16 1476 #define PMU_REG_3P0_OK_VDD3P0_MASK 0x20000u 1477 #define PMU_REG_3P0_OK_VDD3P0_SHIFT 17 1478 #define PMU_REG_3P0_REG_TEST_MASK 0x3C0000u 1479 #define PMU_REG_3P0_REG_TEST_SHIFT 18 1480 #define PMU_REG_3P0_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_REG_TEST_SHIFT))&PMU_REG_3P0_REG_TEST_MASK) 1481 #define PMU_REG_3P0_RSVD2_MASK 0xFFC00000u 1482 #define PMU_REG_3P0_RSVD2_SHIFT 22 1483 #define PMU_REG_3P0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD2_SHIFT))&PMU_REG_3P0_RSVD2_MASK) 1484 /* REG_3P0_SET Bit Fields */ 1485 #define PMU_REG_3P0_SET_ENABLE_LINREG_MASK 0x1u 1486 #define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT 0 1487 #define PMU_REG_3P0_SET_ENABLE_BO_MASK 0x2u 1488 #define PMU_REG_3P0_SET_ENABLE_BO_SHIFT 1 1489 #define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK 0x4u 1490 #define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT 2 1491 #define PMU_REG_3P0_SET_RSVD0_MASK 0x8u 1492 #define PMU_REG_3P0_SET_RSVD0_SHIFT 3 1493 #define PMU_REG_3P0_SET_BO_OFFSET_MASK 0x70u 1494 #define PMU_REG_3P0_SET_BO_OFFSET_SHIFT 4 1495 #define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_BO_OFFSET_SHIFT))&PMU_REG_3P0_SET_BO_OFFSET_MASK) 1496 #define PMU_REG_3P0_SET_VBUS_SEL_MASK 0x80u 1497 #define PMU_REG_3P0_SET_VBUS_SEL_SHIFT 7 1498 #define PMU_REG_3P0_SET_OUTPUT_TRG_MASK 0x1F00u 1499 #define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT 8 1500 #define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_SET_OUTPUT_TRG_MASK) 1501 #define PMU_REG_3P0_SET_RSVD1_MASK 0xE000u 1502 #define PMU_REG_3P0_SET_RSVD1_SHIFT 13 1503 #define PMU_REG_3P0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD1_SHIFT))&PMU_REG_3P0_SET_RSVD1_MASK) 1504 #define PMU_REG_3P0_SET_BO_VDD3P0_MASK 0x10000u 1505 #define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT 16 1506 #define PMU_REG_3P0_SET_OK_VDD3P0_MASK 0x20000u 1507 #define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT 17 1508 #define PMU_REG_3P0_SET_REG_TEST_MASK 0x3C0000u 1509 #define PMU_REG_3P0_SET_REG_TEST_SHIFT 18 1510 #define PMU_REG_3P0_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_REG_TEST_SHIFT))&PMU_REG_3P0_SET_REG_TEST_MASK) 1511 #define PMU_REG_3P0_SET_RSVD2_MASK 0xFFC00000u 1512 #define PMU_REG_3P0_SET_RSVD2_SHIFT 22 1513 #define PMU_REG_3P0_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD2_SHIFT))&PMU_REG_3P0_SET_RSVD2_MASK) 1514 /* REG_3P0_CLR Bit Fields */ 1515 #define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK 0x1u 1516 #define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT 0 1517 #define PMU_REG_3P0_CLR_ENABLE_BO_MASK 0x2u 1518 #define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT 1 1519 #define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK 0x4u 1520 #define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT 2 1521 #define PMU_REG_3P0_CLR_RSVD0_MASK 0x8u 1522 #define PMU_REG_3P0_CLR_RSVD0_SHIFT 3 1523 #define PMU_REG_3P0_CLR_BO_OFFSET_MASK 0x70u 1524 #define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT 4 1525 #define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_3P0_CLR_BO_OFFSET_MASK) 1526 #define PMU_REG_3P0_CLR_VBUS_SEL_MASK 0x80u 1527 #define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT 7 1528 #define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK 0x1F00u 1529 #define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT 8 1530 #define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_CLR_OUTPUT_TRG_MASK) 1531 #define PMU_REG_3P0_CLR_RSVD1_MASK 0xE000u 1532 #define PMU_REG_3P0_CLR_RSVD1_SHIFT 13 1533 #define PMU_REG_3P0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD1_SHIFT))&PMU_REG_3P0_CLR_RSVD1_MASK) 1534 #define PMU_REG_3P0_CLR_BO_VDD3P0_MASK 0x10000u 1535 #define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT 16 1536 #define PMU_REG_3P0_CLR_OK_VDD3P0_MASK 0x20000u 1537 #define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT 17 1538 #define PMU_REG_3P0_CLR_REG_TEST_MASK 0x3C0000u 1539 #define PMU_REG_3P0_CLR_REG_TEST_SHIFT 18 1540 #define PMU_REG_3P0_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_REG_TEST_SHIFT))&PMU_REG_3P0_CLR_REG_TEST_MASK) 1541 #define PMU_REG_3P0_CLR_RSVD2_MASK 0xFFC00000u 1542 #define PMU_REG_3P0_CLR_RSVD2_SHIFT 22 1543 #define PMU_REG_3P0_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD2_SHIFT))&PMU_REG_3P0_CLR_RSVD2_MASK) 1544 /* REG_3P0_TOG Bit Fields */ 1545 #define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK 0x1u 1546 #define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT 0 1547 #define PMU_REG_3P0_TOG_ENABLE_BO_MASK 0x2u 1548 #define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT 1 1549 #define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK 0x4u 1550 #define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT 2 1551 #define PMU_REG_3P0_TOG_RSVD0_MASK 0x8u 1552 #define PMU_REG_3P0_TOG_RSVD0_SHIFT 3 1553 #define PMU_REG_3P0_TOG_BO_OFFSET_MASK 0x70u 1554 #define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT 4 1555 #define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_3P0_TOG_BO_OFFSET_MASK) 1556 #define PMU_REG_3P0_TOG_VBUS_SEL_MASK 0x80u 1557 #define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT 7 1558 #define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK 0x1F00u 1559 #define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT 8 1560 #define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_TOG_OUTPUT_TRG_MASK) 1561 #define PMU_REG_3P0_TOG_RSVD1_MASK 0xE000u 1562 #define PMU_REG_3P0_TOG_RSVD1_SHIFT 13 1563 #define PMU_REG_3P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD1_SHIFT))&PMU_REG_3P0_TOG_RSVD1_MASK) 1564 #define PMU_REG_3P0_TOG_BO_VDD3P0_MASK 0x10000u 1565 #define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT 16 1566 #define PMU_REG_3P0_TOG_OK_VDD3P0_MASK 0x20000u 1567 #define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT 17 1568 #define PMU_REG_3P0_TOG_REG_TEST_MASK 0x3C0000u 1569 #define PMU_REG_3P0_TOG_REG_TEST_SHIFT 18 1570 #define PMU_REG_3P0_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_REG_TEST_SHIFT))&PMU_REG_3P0_TOG_REG_TEST_MASK) 1571 #define PMU_REG_3P0_TOG_RSVD2_MASK 0xFFC00000u 1572 #define PMU_REG_3P0_TOG_RSVD2_SHIFT 22 1573 #define PMU_REG_3P0_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD2_SHIFT))&PMU_REG_3P0_TOG_RSVD2_MASK) 1574 /* REF Bit Fields */ 1575 #define PMU_REF_REFTOP_PWD_MASK 0x1u 1576 #define PMU_REF_REFTOP_PWD_SHIFT 0 1577 #define PMU_REF_REFTOP_PWDVBGUP_MASK 0x2u 1578 #define PMU_REF_REFTOP_PWDVBGUP_SHIFT 1 1579 #define PMU_REF_REFTOP_LOWPOWER_MASK 0x4u 1580 #define PMU_REF_REFTOP_LOWPOWER_SHIFT 2 1581 #define PMU_REF_REFTOP_SELFBIASOFF_MASK 0x8u 1582 #define PMU_REF_REFTOP_SELFBIASOFF_SHIFT 3 1583 #define PMU_REF_REFTOP_VBGADJ_MASK 0x70u 1584 #define PMU_REF_REFTOP_VBGADJ_SHIFT 4 1585 #define PMU_REF_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_VBGADJ_SHIFT))&PMU_REF_REFTOP_VBGADJ_MASK) 1586 #define PMU_REF_REFTOP_VBGUP_MASK 0x80u 1587 #define PMU_REF_REFTOP_VBGUP_SHIFT 7 1588 #define PMU_REF_REFTOP_BIAS_TST_MASK 0x300u 1589 #define PMU_REF_REFTOP_BIAS_TST_SHIFT 8 1590 #define PMU_REF_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_BIAS_TST_SHIFT))&PMU_REF_REFTOP_BIAS_TST_MASK) 1591 #define PMU_REF_LPBG_SEL_MASK 0x400u 1592 #define PMU_REF_LPBG_SEL_SHIFT 10 1593 #define PMU_REF_LPBG_TEST_MASK 0x800u 1594 #define PMU_REF_LPBG_TEST_SHIFT 11 1595 #define PMU_REF_REFTOP_IBIAS_OFF_MASK 0x1000u 1596 #define PMU_REF_REFTOP_IBIAS_OFF_SHIFT 12 1597 #define PMU_REF_REFTOP_LINREGREF_EN_MASK 0x2000u 1598 #define PMU_REF_REFTOP_LINREGREF_EN_SHIFT 13 1599 #define PMU_REF_RSVD1_MASK 0xFFFFC000u 1600 #define PMU_REF_RSVD1_SHIFT 14 1601 #define PMU_REF_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_RSVD1_SHIFT))&PMU_REF_RSVD1_MASK) 1602 /* REF_SET Bit Fields */ 1603 #define PMU_REF_SET_REFTOP_PWD_MASK 0x1u 1604 #define PMU_REF_SET_REFTOP_PWD_SHIFT 0 1605 #define PMU_REF_SET_REFTOP_PWDVBGUP_MASK 0x2u 1606 #define PMU_REF_SET_REFTOP_PWDVBGUP_SHIFT 1 1607 #define PMU_REF_SET_REFTOP_LOWPOWER_MASK 0x4u 1608 #define PMU_REF_SET_REFTOP_LOWPOWER_SHIFT 2 1609 #define PMU_REF_SET_REFTOP_SELFBIASOFF_MASK 0x8u 1610 #define PMU_REF_SET_REFTOP_SELFBIASOFF_SHIFT 3 1611 #define PMU_REF_SET_REFTOP_VBGADJ_MASK 0x70u 1612 #define PMU_REF_SET_REFTOP_VBGADJ_SHIFT 4 1613 #define PMU_REF_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_VBGADJ_SHIFT))&PMU_REF_SET_REFTOP_VBGADJ_MASK) 1614 #define PMU_REF_SET_REFTOP_VBGUP_MASK 0x80u 1615 #define PMU_REF_SET_REFTOP_VBGUP_SHIFT 7 1616 #define PMU_REF_SET_REFTOP_BIAS_TST_MASK 0x300u 1617 #define PMU_REF_SET_REFTOP_BIAS_TST_SHIFT 8 1618 #define PMU_REF_SET_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_BIAS_TST_SHIFT))&PMU_REF_SET_REFTOP_BIAS_TST_MASK) 1619 #define PMU_REF_SET_LPBG_SEL_MASK 0x400u 1620 #define PMU_REF_SET_LPBG_SEL_SHIFT 10 1621 #define PMU_REF_SET_LPBG_TEST_MASK 0x800u 1622 #define PMU_REF_SET_LPBG_TEST_SHIFT 11 1623 #define PMU_REF_SET_REFTOP_IBIAS_OFF_MASK 0x1000u 1624 #define PMU_REF_SET_REFTOP_IBIAS_OFF_SHIFT 12 1625 #define PMU_REF_SET_REFTOP_LINREGREF_EN_MASK 0x2000u 1626 #define PMU_REF_SET_REFTOP_LINREGREF_EN_SHIFT 13 1627 #define PMU_REF_SET_RSVD1_MASK 0xFFFFC000u 1628 #define PMU_REF_SET_RSVD1_SHIFT 14 1629 #define PMU_REF_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_RSVD1_SHIFT))&PMU_REF_SET_RSVD1_MASK) 1630 /* REF_CLR Bit Fields */ 1631 #define PMU_REF_CLR_REFTOP_PWD_MASK 0x1u 1632 #define PMU_REF_CLR_REFTOP_PWD_SHIFT 0 1633 #define PMU_REF_CLR_REFTOP_PWDVBGUP_MASK 0x2u 1634 #define PMU_REF_CLR_REFTOP_PWDVBGUP_SHIFT 1 1635 #define PMU_REF_CLR_REFTOP_LOWPOWER_MASK 0x4u 1636 #define PMU_REF_CLR_REFTOP_LOWPOWER_SHIFT 2 1637 #define PMU_REF_CLR_REFTOP_SELFBIASOFF_MASK 0x8u 1638 #define PMU_REF_CLR_REFTOP_SELFBIASOFF_SHIFT 3 1639 #define PMU_REF_CLR_REFTOP_VBGADJ_MASK 0x70u 1640 #define PMU_REF_CLR_REFTOP_VBGADJ_SHIFT 4 1641 #define PMU_REF_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_VBGADJ_SHIFT))&PMU_REF_CLR_REFTOP_VBGADJ_MASK) 1642 #define PMU_REF_CLR_REFTOP_VBGUP_MASK 0x80u 1643 #define PMU_REF_CLR_REFTOP_VBGUP_SHIFT 7 1644 #define PMU_REF_CLR_REFTOP_BIAS_TST_MASK 0x300u 1645 #define PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT 8 1646 #define PMU_REF_CLR_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT))&PMU_REF_CLR_REFTOP_BIAS_TST_MASK) 1647 #define PMU_REF_CLR_LPBG_SEL_MASK 0x400u 1648 #define PMU_REF_CLR_LPBG_SEL_SHIFT 10 1649 #define PMU_REF_CLR_LPBG_TEST_MASK 0x800u 1650 #define PMU_REF_CLR_LPBG_TEST_SHIFT 11 1651 #define PMU_REF_CLR_REFTOP_IBIAS_OFF_MASK 0x1000u 1652 #define PMU_REF_CLR_REFTOP_IBIAS_OFF_SHIFT 12 1653 #define PMU_REF_CLR_REFTOP_LINREGREF_EN_MASK 0x2000u 1654 #define PMU_REF_CLR_REFTOP_LINREGREF_EN_SHIFT 13 1655 #define PMU_REF_CLR_RSVD1_MASK 0xFFFFC000u 1656 #define PMU_REF_CLR_RSVD1_SHIFT 14 1657 #define PMU_REF_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_RSVD1_SHIFT))&PMU_REF_CLR_RSVD1_MASK) 1658 /* REF_TOG Bit Fields */ 1659 #define PMU_REF_TOG_REFTOP_PWD_MASK 0x1u 1660 #define PMU_REF_TOG_REFTOP_PWD_SHIFT 0 1661 #define PMU_REF_TOG_REFTOP_PWDVBGUP_MASK 0x2u 1662 #define PMU_REF_TOG_REFTOP_PWDVBGUP_SHIFT 1 1663 #define PMU_REF_TOG_REFTOP_LOWPOWER_MASK 0x4u 1664 #define PMU_REF_TOG_REFTOP_LOWPOWER_SHIFT 2 1665 #define PMU_REF_TOG_REFTOP_SELFBIASOFF_MASK 0x8u 1666 #define PMU_REF_TOG_REFTOP_SELFBIASOFF_SHIFT 3 1667 #define PMU_REF_TOG_REFTOP_VBGADJ_MASK 0x70u 1668 #define PMU_REF_TOG_REFTOP_VBGADJ_SHIFT 4 1669 #define PMU_REF_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_VBGADJ_SHIFT))&PMU_REF_TOG_REFTOP_VBGADJ_MASK) 1670 #define PMU_REF_TOG_REFTOP_VBGUP_MASK 0x80u 1671 #define PMU_REF_TOG_REFTOP_VBGUP_SHIFT 7 1672 #define PMU_REF_TOG_REFTOP_BIAS_TST_MASK 0x300u 1673 #define PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT 8 1674 #define PMU_REF_TOG_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT))&PMU_REF_TOG_REFTOP_BIAS_TST_MASK) 1675 #define PMU_REF_TOG_LPBG_SEL_MASK 0x400u 1676 #define PMU_REF_TOG_LPBG_SEL_SHIFT 10 1677 #define PMU_REF_TOG_LPBG_TEST_MASK 0x800u 1678 #define PMU_REF_TOG_LPBG_TEST_SHIFT 11 1679 #define PMU_REF_TOG_REFTOP_IBIAS_OFF_MASK 0x1000u 1680 #define PMU_REF_TOG_REFTOP_IBIAS_OFF_SHIFT 12 1681 #define PMU_REF_TOG_REFTOP_LINREGREF_EN_MASK 0x2000u 1682 #define PMU_REF_TOG_REFTOP_LINREGREF_EN_SHIFT 13 1683 #define PMU_REF_TOG_RSVD1_MASK 0xFFFFC000u 1684 #define PMU_REF_TOG_RSVD1_SHIFT 14 1685 #define PMU_REF_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_RSVD1_SHIFT))&PMU_REF_TOG_RSVD1_MASK) 1686 /* LOWPWR_CTRL Bit Fields */ 1687 #define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK 0x3u 1688 #define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT 0 1689 #define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK) 1690 #define PMU_LOWPWR_CTRL_RSVD0_MASK 0xFCu 1691 #define PMU_LOWPWR_CTRL_RSVD0_SHIFT 2 1692 #define PMU_LOWPWR_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_RSVD0_MASK) 1693 #define PMU_LOWPWR_CTRL_L1_PWRGATE_MASK 0x100u 1694 #define PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT 8 1695 #define PMU_LOWPWR_CTRL_L2_PWRGATE_MASK 0x200u 1696 #define PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT 9 1697 #define PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK 0x400u 1698 #define PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT 10 1699 #define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK 0x800u 1700 #define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT 11 1701 #define PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK 0x1000u 1702 #define PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT 12 1703 #define PMU_LOWPWR_CTRL_GPU_PWRGATE_MASK 0x2000u 1704 #define PMU_LOWPWR_CTRL_GPU_PWRGATE_SHIFT 13 1705 #define PMU_LOWPWR_CTRL_CONTROL0_MASK 0xFFC000u 1706 #define PMU_LOWPWR_CTRL_CONTROL0_SHIFT 14 1707 #define PMU_LOWPWR_CTRL_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CONTROL0_MASK) 1708 #define PMU_LOWPWR_CTRL_CONTROL1_MASK 0xFF000000u 1709 #define PMU_LOWPWR_CTRL_CONTROL1_SHIFT 24 1710 #define PMU_LOWPWR_CTRL_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CONTROL1_MASK) 1711 /* LOWPWR_CTRL_SET Bit Fields */ 1712 #define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK 0x3u 1713 #define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT 0 1714 #define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK) 1715 #define PMU_LOWPWR_CTRL_SET_RSVD0_MASK 0xFCu 1716 #define PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT 2 1717 #define PMU_LOWPWR_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_SET_RSVD0_MASK) 1718 #define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK 0x100u 1719 #define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT 8 1720 #define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK 0x200u 1721 #define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT 9 1722 #define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK 0x400u 1723 #define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT 10 1724 #define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK 0x800u 1725 #define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT 11 1726 #define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK 0x1000u 1727 #define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT 12 1728 #define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK 0x2000u 1729 #define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT 13 1730 #define PMU_LOWPWR_CTRL_SET_CONTROL0_MASK 0xFFC000u 1731 #define PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT 14 1732 #define PMU_LOWPWR_CTRL_SET_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL0_MASK) 1733 #define PMU_LOWPWR_CTRL_SET_CONTROL1_MASK 0xFF000000u 1734 #define PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT 24 1735 #define PMU_LOWPWR_CTRL_SET_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL1_MASK) 1736 /* LOWPWR_CTRL_CLR Bit Fields */ 1737 #define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK 0x3u 1738 #define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT 0 1739 #define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK) 1740 #define PMU_LOWPWR_CTRL_CLR_RSVD0_MASK 0xFCu 1741 #define PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT 2 1742 #define PMU_LOWPWR_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_CLR_RSVD0_MASK) 1743 #define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK 0x100u 1744 #define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT 8 1745 #define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK 0x200u 1746 #define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT 9 1747 #define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK 0x400u 1748 #define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT 10 1749 #define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK 0x800u 1750 #define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT 11 1751 #define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK 0x1000u 1752 #define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT 12 1753 #define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK 0x2000u 1754 #define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT 13 1755 #define PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK 0xFFC000u 1756 #define PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT 14 1757 #define PMU_LOWPWR_CTRL_CLR_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK) 1758 #define PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK 0xFF000000u 1759 #define PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT 24 1760 #define PMU_LOWPWR_CTRL_CLR_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK) 1761 /* LOWPWR_CTRL_TOG Bit Fields */ 1762 #define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK 0x3u 1763 #define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT 0 1764 #define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK) 1765 #define PMU_LOWPWR_CTRL_TOG_RSVD0_MASK 0xFCu 1766 #define PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT 2 1767 #define PMU_LOWPWR_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_TOG_RSVD0_MASK) 1768 #define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK 0x100u 1769 #define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT 8 1770 #define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK 0x200u 1771 #define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT 9 1772 #define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK 0x400u 1773 #define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT 10 1774 #define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK 0x800u 1775 #define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT 11 1776 #define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK 0x1000u 1777 #define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT 12 1778 #define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK 0x2000u 1779 #define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT 13 1780 #define PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK 0xFFC000u 1781 #define PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT 14 1782 #define PMU_LOWPWR_CTRL_TOG_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK) 1783 #define PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK 0xFF000000u 1784 #define PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT 24 1785 #define PMU_LOWPWR_CTRL_TOG_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK) 1786 1787 1788 /* HW_ANADIG_TEMPSENSE0 Bit Fields */ 1789 #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu 1790 #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0 1791 #define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK) 1792 #define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK 0x3FE00u 1793 #define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT 9 1794 #define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK) 1795 #define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK 0x7FC0000u 1796 #define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT 18 1797 #define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK) 1798 #define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK 0xF8000000u 1799 #define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT 27 1800 #define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK) 1801 /* HW_ANADIG_TEMPSENSE0_SET Bit Fields */ 1802 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK 0x1FFu 1803 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT 0 1804 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK) 1805 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK 0x3FE00u 1806 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT 9 1807 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK) 1808 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK 0x7FC0000u 1809 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT 18 1810 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK) 1811 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK 0xF8000000u 1812 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT 27 1813 #define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK) 1814 /* HW_ANADIG_TEMPSENSE0_CLR Bit Fields */ 1815 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK 0x1FFu 1816 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT 0 1817 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK) 1818 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK 0x3FE00u 1819 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT 9 1820 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK) 1821 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK 0x7FC0000u 1822 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT 18 1823 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK) 1824 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK 0xF8000000u 1825 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT 27 1826 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK) 1827 /* HW_ANADIG_TEMPSENSE0_TOG Bit Fields */ 1828 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK 0x1FFu 1829 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT 0 1830 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK) 1831 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK 0x3FE00u 1832 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT 9 1833 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK) 1834 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK 0x7FC0000u 1835 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT 18 1836 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK) 1837 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK 0xF8000000u 1838 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT 27 1839 #define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK) 1840 /* HW_ANADIG_TEMPSENSE1 Bit Fields */ 1841 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK 0x1FFu 1842 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT 0 1843 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) 1844 #define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK 0x200u 1845 #define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_SHIFT 9 1846 #define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK 0x400u 1847 #define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_SHIFT 10 1848 #define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK 0x800u 1849 #define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_SHIFT 11 1850 #define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK 0xF000u 1851 #define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT 12 1852 #define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK) 1853 #define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK 0xFFFF0000u 1854 #define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT 16 1855 #define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK) 1856 /* HW_ANADIG_TEMPSENSE1_SET Bit Fields */ 1857 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK 0x1FFu 1858 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT 0 1859 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK) 1860 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_MASK 0x200u 1861 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_SHIFT 9 1862 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_MASK 0x400u 1863 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_SHIFT 10 1864 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_MASK 0x800u 1865 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_SHIFT 11 1866 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK 0xF000u 1867 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT 12 1868 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK) 1869 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK 0xFFFF0000u 1870 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT 16 1871 #define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK) 1872 /* HW_ANADIG_TEMPSENSE1_CLR Bit Fields */ 1873 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK 0x1FFu 1874 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT 0 1875 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK) 1876 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_MASK 0x200u 1877 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_SHIFT 9 1878 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_MASK 0x400u 1879 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_SHIFT 10 1880 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_MASK 0x800u 1881 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_SHIFT 11 1882 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK 0xF000u 1883 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT 12 1884 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK) 1885 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK 0xFFFF0000u 1886 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT 16 1887 #define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK) 1888 /* HW_ANADIG_TEMPSENSE1_TOG Bit Fields */ 1889 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK 0x1FFu 1890 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT 0 1891 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK) 1892 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_MASK 0x200u 1893 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_SHIFT 9 1894 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_MASK 0x400u 1895 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_SHIFT 10 1896 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_MASK 0x800u 1897 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_SHIFT 11 1898 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK 0xF000u 1899 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT 12 1900 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK) 1901 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK 0xFFFF0000u 1902 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT 16 1903 #define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK) 1904 /* HW_ANADIG_TEMPSENSE_TRIM Bit Fields */ 1905 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK 0x1Fu 1906 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT 0 1907 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK) 1908 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK 0x60u 1909 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT 5 1910 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK) 1911 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_MASK 0x80u 1912 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_SHIFT 7 1913 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK 0x1FF00u 1914 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT 8 1915 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK) 1916 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK 0xE0000u 1917 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT 17 1918 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK) 1919 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK 0xF00000u 1920 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT 20 1921 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK) 1922 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK 0x1F000000u 1923 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT 24 1924 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK) 1925 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK 0xE0000000u 1926 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT 29 1927 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK) 1928 /* HW_ANADIG_TEMPSENSE_TRIM_SET Bit Fields */ 1929 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK 0x1Fu 1930 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT 0 1931 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK) 1932 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK 0x60u 1933 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT 5 1934 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK) 1935 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_MASK 0x80u 1936 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_SHIFT 7 1937 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK 0x1FF00u 1938 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT 8 1939 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK) 1940 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK 0xE0000u 1941 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT 17 1942 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK) 1943 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK 0xF00000u 1944 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT 20 1945 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK) 1946 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK 0x1F000000u 1947 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT 24 1948 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK) 1949 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK 0xE0000000u 1950 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT 29 1951 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK) 1952 /* HW_ANADIG_TEMPSENSE_TRIM_CLR Bit Fields */ 1953 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK 0x1Fu 1954 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT 0 1955 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK) 1956 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK 0x60u 1957 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT 5 1958 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK) 1959 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_MASK 0x80u 1960 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_SHIFT 7 1961 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK 0x1FF00u 1962 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT 8 1963 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK) 1964 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK 0xE0000u 1965 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT 17 1966 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK) 1967 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK 0xF00000u 1968 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT 20 1969 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK) 1970 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK 0x1F000000u 1971 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT 24 1972 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK) 1973 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK 0xE0000000u 1974 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT 29 1975 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK) 1976 /* HW_ANADIG_TEMPSENSE_TRIM_TOG Bit Fields */ 1977 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK 0x1Fu 1978 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT 0 1979 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK) 1980 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK 0x60u 1981 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT 5 1982 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK) 1983 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_MASK 0x80u 1984 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_SHIFT 7 1985 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK 0x1FF00u 1986 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT 8 1987 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK) 1988 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK 0xE0000u 1989 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT 17 1990 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK) 1991 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK 0xF00000u 1992 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT 20 1993 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK) 1994 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK 0x1F000000u 1995 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT 24 1996 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK) 1997 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK 0xE0000000u 1998 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29 1999 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK) 2000 2001 2002 #define CCM_GPR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i)) 2003 #define CCM_OBSERVE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i)) 2004 #define CCM_SCTRL(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i)) 2005 #define CCM_CCGR(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i)) 2006 #define CCM_ROOT_TARGET(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i)) 2007 2008 #define CCM_GPR_SET(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 4) 2009 #define CCM_OBSERVE_SET(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4) 2010 #define CCM_SCTRL_SET(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4) 2011 #define CCM_CCGR_SET(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 4) 2012 #define CCM_ROOT_TARGET_SET(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4) 2013 2014 #define CCM_GPR_CLR(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 8) 2015 #define CCM_OBSERVE_CLR(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8) 2016 #define CCM_SCTRL_CLR(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8) 2017 #define CCM_CCGR_CLR(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 8) 2018 #define CCM_ROOT_TARGET_CLR(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8) 2019 2020 #define CCM_GPR_TOGGLE(i) (CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 12) 2021 #define CCM_OBSERVE_TOGGLE(i) (CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12) 2022 #define CCM_SCTRL_TOGGLE(i) (CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12) 2023 #define CCM_CCGR_TOGGLE(i) (CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 12) 2024 #define CCM_ROOT_TARGET_TOGGLE(i) (CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12) 2025 2026 #define HW_CCM_GPR_WR(i, v) writel((v), CCM_GPR(i)) 2027 #define HW_CCM_CCM_OBSERVE_WR(i, v) writel((v), CCM_OBSERVE(i)) 2028 #define HW_CCM_SCTRL_WR(i, v) writel((v), CCM_SCTRL(i)) 2029 #define HW_CCM_CCGR_WR(i, v) writel((v), CCM_CCGR(i)) 2030 #define HW_CCM_ROOT_TARGET_WR(i, v) writel((v), CCM_ROOT_TARGET(i)) 2031 2032 #define HW_CCM_GPR_RD(i) readl(CCM_GPR(i)) 2033 #define HW_CCM_CCM_OBSERVE_RD(i) readl(CCM_OBSERVE(i)) 2034 #define HW_CCM_SCTRL_RD(i) readl(CCM_SCTRL(i)) 2035 #define HW_CCM_CCGR_RD(i) readl(CCM_CCGR(i)) 2036 #define HW_CCM_ROOT_TARGET_RD(i) readl(CCM_ROOT_TARGET(i)) 2037 2038 #define HW_CCM_GPR_SET(i, v) writel((v), CCM_GPR_SET(i)) 2039 #define HW_CCM_CCM_OBSERVE_SET(i, v) writel((v), CCM_CCM_OBSERVE_SET(i)) 2040 #define HW_CCM_SCTRL_SET(i, v) writel((v), CCM_SCTRL_SET(i)) 2041 #define HW_CCM_CCGR_SET(i, v) writel((v), CCM_CCGR_SET(i)) 2042 #define HW_CCM_ROOT_TARGET_SET(i, v) writel((v), CCM_ROOT_TARGET_SET(i)) 2043 2044 #define HW_CCM_GPR_CLR(i, v) writel((v), CCM_GPR_CLR(i)) 2045 #define HW_CCM_CCM_OBSERVE_CLR(i, v) writel((v), CCM_CCM_OBSERVE_CLR(i)) 2046 #define HW_CCM_SCTRL_CLR(i, v) writel((v), CCM_SCTRL_CLR(i)) 2047 #define HW_CCM_CCGR_CLR(i, v) writel((v), CCM_CCGR_CLR(i)) 2048 #define HW_CCM_ROOT_TARGET_CLR(i, v) writel((v), CCM_ROOT_TARGET_CLR(i)) 2049 2050 #define HW_CCM_GPR_TOGGLE(i, v) writel((v), CCM_GPR_TOGGLE(i)) 2051 #define HW_CCM_CCM_OBSERVE_TOGGLE(i, v) writel((v), CCM_CCM_OBSERVE_TOGGLE(i)) 2052 #define HW_CCM_SCTRL_TOGGLE(i, v) writel((v), CCM_SCTRL_TOGGLE(i)) 2053 #define HW_CCM_CCGR_TOGGLE(i, v) writel((v), CCM_CCGR_TOGGLE(i)) 2054 #define HW_CCM_ROOT_TARGET_TOGGLE(i, v) writel((v), CCM_ROOT_TARGET_TOGGLE(i)) 2055 2056 #define CCM_CLK_ON_MSK 0x03 2057 #define CCM_CLK_ON_N_N 0x00 /* Domain clocks not needed */ 2058 #define CCM_CLK_ON_R_W 0x02 /* Domain clocks needed when in RUN and WAIT */ 2059 2060 /* CCGR Mapping */ 2061 #define CCGR_IDX_DDR 19 /* CCM_CCGR19 */ 2062 2063 #define CCM_ROOT_TGT_POST_DIV_SHIFT 0 2064 #define CCM_ROOT_TGT_PRE_DIV_SHIFT 15 2065 #define CCM_ROOT_TGT_MUX_SHIFT 24 2066 #define CCM_ROOT_TGT_ENABLE_SHIFT 28 2067 #define CCM_ROOT_TGT_POST_DIV_MSK 0x3F 2068 #define CCM_ROOT_TGT_PRE_DIV_MSK (0x07 << CCM_ROOT_TGT_PRE_DIV_SHIFT) 2069 #define CCM_ROOT_TGT_MUX_MSK (0x07 << CCM_ROOT_TGT_MUX_SHIFT) 2070 #define CCM_ROOT_TGT_ENABLE_MSK (0x01 << CCM_ROOT_TGT_ENABLE_SHIFT) 2071 2072 #define CCM_ROOT_TGT_POST_DIV(x) ((((x) - 1) << CCM_ROOT_TGT_POST_DIV_SHIFT) & CCM_ROOT_TGT_POST_DIV_MSK) 2073 #define CCM_ROOT_TGT_PRE_DIV(x) ((((x) - 1) << CCM_ROOT_TGT_PRE_DIV_SHIFT) & CCM_ROOT_TGT_PRE_DIV_MSK) 2074 #define CCM_ROOT_TGT_MUX_TO(x) ((((x) - 1) << CCM_ROOT_TGT_MUX_SHIFT) & CCM_ROOT_TGT_MUX_MSK) 2075 2076 /* 2077 * Field values definition for clock slice TARGET register 2078 */ 2079 2080 #define CLK_ROOT_ON 0x10000000 2081 #define CLK_ROOT_OFF 0x0 2082 #define CLK_ROOT_ENABLE_MASK 0x10000000 2083 #define CLK_ROOT_ENABLE_SHIFT 28 2084 2085 #define CLK_ROOT_ALT0 0x00000000 2086 #define CLK_ROOT_ALT1 0x01000000 2087 #define CLK_ROOT_ALT2 0x02000000 2088 #define CLK_ROOT_ALT3 0x03000000 2089 #define CLK_ROOT_ALT4 0x04000000 2090 #define CLK_ROOT_ALT5 0x05000000 2091 #define CLK_ROOT_ALT6 0x06000000 2092 #define CLK_ROOT_ALT7 0x07000000 2093 2094 2095 #define DRAM_CLK_ROOT_POST_DIV_MASK 0x00000007 2096 #define CLK_ROOT_POST_DIV_MASK 0x0000003f 2097 #define CLK_ROOT_POST_DIV_SHIFT 0 2098 #define CLK_ROOT_POST_DIV(n) ((n << CLK_ROOT_POST_DIV_SHIFT) & CLK_ROOT_POST_DIV_MASK) 2099 2100 #define CLK_ROOT_AUTO_DIV_MASK 0x00000700 2101 #define CLK_ROOT_AUTO_DIV_SHIFT 8 2102 #define CLK_ROOT_AUTO_DIV(n) ((n << CLK_ROOT_AUTO_DIV_SHIFT) & CLK_ROOT_AUTO_DIV_MASK) 2103 2104 #define CLK_ROOT_AUTO_EN_MASK 0x00001000 2105 #define CLK_ROOT_AUTO_EN 0x00001000 2106 2107 #define CLK_ROOT_PRE_DIV_MASK 0x00070000 2108 #define CLK_ROOT_PRE_DIV_SHIFT 16 2109 #define CLK_ROOT_PRE_DIV(n) ((n << CLK_ROOT_PRE_DIV_SHIFT) & CLK_ROOT_PRE_DIV_MASK) 2110 2111 #define CLK_ROOT_MUX_MASK 0x07000000 2112 #define CLK_ROOT_MUX_SHIFT 24 2113 2114 #define CLK_ROOT_EN_MASK 0x10000000 2115 2116 #define CLK_ROOT_AUTO_ON 0x00001000 2117 #define CLK_ROOT_AUTO_OFF 0x0 2118 2119 /* ARM_A7_CLK_ROOT */ 2120 #define ARM_A7_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2121 #define ARM_A7_CLK_ROOT_FROM_PLL_ARM_MAIN_800M_CLK 0x01000000 2122 #define ARM_A7_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x03000000 2123 #define ARM_A7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2124 #define ARM_A7_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x05000000 2125 #define ARM_A7_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x02000000 2126 #define ARM_A7_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 2127 #define ARM_A7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2128 2129 /* ARM_M4_CLK_ROOT */ 2130 #define ARM_M4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2131 #define ARM_M4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 2132 #define ARM_M4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2133 #define ARM_M4_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x03000000 2134 #define ARM_M4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x02000000 2135 #define ARM_M4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2136 #define ARM_M4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2137 #define ARM_M4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2138 2139 /* ARM_M0_CLK_ROOT */ 2140 #define ARM_M0_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2141 #define ARM_M0_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 2142 #define ARM_M0_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 2143 #define ARM_M0_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x03000000 2144 #define ARM_M0_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x02000000 2145 #define ARM_M0_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2146 #define ARM_M0_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2147 #define ARM_M0_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2148 2149 /* MAIN_AXI_CLK_ROOT */ 2150 #define MAIN_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2151 #define MAIN_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2152 #define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000 2153 #define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x04000000 2154 #define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 2155 #define MAIN_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000 2156 #define MAIN_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2157 #define MAIN_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2158 2159 /* DISP_AXI_CLK_ROOT */ 2160 #define DISP_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2161 #define DISP_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2162 #define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000 2163 #define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x04000000 2164 #define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x05000000 2165 #define DISP_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000 2166 #define DISP_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 2167 #define DISP_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2168 2169 /* ENET_AXI_CLK_ROOT */ 2170 #define ENET_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2171 #define ENET_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2172 #define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x04000000 2173 #define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x01000000 2174 #define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000 2175 #define ENET_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000 2176 #define ENET_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2177 #define ENET_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2178 2179 /* NAND_USDHC_BUS_CLK_ROOT */ 2180 #define NAND_USDHC_BUS_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2181 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2182 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x03000000 2183 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x01000000 2184 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x04000000 2185 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x05000000 2186 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 2187 #define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000 2188 2189 /* AHB_CLK_ROOT */ 2190 #define AHB_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2191 #define AHB_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2192 #define AHB_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x03000000 2193 #define AHB_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2194 #define AHB_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 2195 #define AHB_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 2196 #define AHB_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2197 #define AHB_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 2198 2199 /* DRAM_PHYM_CLK_ROOT */ 2200 #define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x00000000 2201 #define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_PHYM_ALT_CLK_ROOT 0x01000000 2202 2203 /* DRAM_CLK_ROOT */ 2204 #define DRAM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x00000000 2205 #define DRAM_CLK_ROOT_FROM_PLL_DRAM_ALT_CLK_ROOT 0x01000000 2206 2207 /* DRAM_PHYM_ALT_CLK_ROOT */ 2208 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2209 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x01000000 2210 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x02000000 2211 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x05000000 2212 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 2213 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 2214 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2215 #define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000 2216 2217 /* DRAM_ALT_CLK_ROOT */ 2218 #define DRAM_ALT_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2219 #define DRAM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x01000000 2220 #define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x02000000 2221 #define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x05000000 2222 #define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x07000000 2223 #define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 2224 #define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x04000000 2225 #define DRAM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 2226 2227 /* USB_HSIC_CLK_ROOT */ 2228 #define USB_HSIC_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2229 #define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000 2230 #define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x03000000 2231 #define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 2232 #define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x05000000 2233 #define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 2234 #define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 2235 #define USB_HSIC_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x02000000 2236 2237 /* PCIE_CTRL_CLK_ROOT */ 2238 #define PCIE_CTRL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2239 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 2240 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x02000000 2241 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x06000000 2242 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x03000000 2243 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x07000000 2244 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000 2245 #define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x01000000 2246 2247 /* PCIE_PHY_CLK_ROOT */ 2248 #define PCIE_PHY_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2249 #define PCIE_PHY_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x07000000 2250 #define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x02000000 2251 #define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2252 #define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_1 0x03000000 2253 #define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_2 0x04000000 2254 #define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 2255 #define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 2256 2257 /* EPDC_PIXEL_CLK_ROOT */ 2258 #define EPDC_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2259 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2260 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 2261 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000 2262 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x04000000 2263 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x05000000 2264 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x06000000 2265 #define EPDC_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2266 2267 /* LCDIF_PIXEL_CLK_ROOT */ 2268 #define LCDIF_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2269 #define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2270 #define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 2271 #define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 2272 #define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x01000000 2273 #define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2274 #define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2275 #define LCDIF_PIXEL_CLK_ROOT_FROM_EXT_CLK_3 0x03000000 2276 2277 /* MIPI_DSI_EXTSER_CLK_ROOT */ 2278 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2279 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x05000000 2280 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 2281 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK 0x04000000 2282 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x02000000 2283 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x01000000 2284 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000 2285 #define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2286 2287 /* MIPI_CSI_WARP_CLK_ROOT */ 2288 #define MIPI_CSI_WARP_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2289 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x05000000 2290 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 2291 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK 0x04000000 2292 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x02000000 2293 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x01000000 2294 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000 2295 #define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2296 2297 /* MIPI_DPHY_REF_CLK_ROOT */ 2298 #define MIPI_DPHY_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2299 #define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2300 #define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 2301 #define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x03000000 2302 #define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2303 #define MIPI_DPHY_REF_CLK_ROOT_FROM_REF_1M_CLK 0x04000000 2304 #define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2305 #define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 2306 2307 /* SAI1_CLK_ROOT */ 2308 #define SAI1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2309 #define SAI1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2310 #define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2311 #define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 2312 #define SAI1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 2313 #define SAI1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 2314 #define SAI1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 2315 #define SAI1_CLK_ROOT_FROM_EXT_CLK_2 0x07000000 2316 2317 /* SAI2_CLK_ROOT */ 2318 #define SAI2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2319 #define SAI2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2320 #define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2321 #define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 2322 #define SAI2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 2323 #define SAI2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 2324 #define SAI2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 2325 #define SAI2_CLK_ROOT_FROM_EXT_CLK_2 0x07000000 2326 2327 /* SAI3_CLK_ROOT */ 2328 #define SAI3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2329 #define SAI3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2330 #define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2331 #define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 2332 #define SAI3_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 2333 #define SAI3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 2334 #define SAI3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 2335 #define SAI3_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 2336 2337 /* SPDIF_CLK_ROOT */ 2338 #define SPDIF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2339 #define SPDIF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2340 #define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2341 #define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 2342 #define SPDIF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 2343 #define SPDIF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 2344 #define SPDIF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 2345 #define SPDIF_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 2346 2347 /* ENET1_REF_CLK_ROOT */ 2348 #define ENET1_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2349 #define ENET1_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x04000000 2350 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 2351 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 2352 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 2353 #define ENET1_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2354 #define ENET1_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2355 #define ENET1_REF_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 2356 2357 /* ENET1_TIME_CLK_ROOT */ 2358 #define ENET1_TIME_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2359 #define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2360 #define ENET1_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 2361 #define ENET1_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2362 #define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_1 0x03000000 2363 #define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_2 0x04000000 2364 #define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 2365 #define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 2366 2367 /* ENET2_REF_CLK_ROOT */ 2368 #define ENET2_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2369 #define ENET2_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x04000000 2370 #define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000 2371 #define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 2372 #define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000 2373 #define ENET2_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2374 #define ENET2_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2375 #define ENET2_REF_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 2376 2377 /* ENET2_TIME_CLK_ROOT */ 2378 #define ENET2_TIME_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2379 #define ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2380 #define ENET2_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000 2381 #define ENET2_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2382 #define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_1 0x03000000 2383 #define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_2 0x04000000 2384 #define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 2385 #define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 2386 2387 /* ENET_PHY_REF_CLK_ROOT */ 2388 #define ENET_PHY_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2389 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000 2390 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x07000000 2391 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x03000000 2392 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 2393 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000 2394 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2395 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2396 2397 /* EIM_CLK_ROOT */ 2398 #define EIM_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2399 #define EIM_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2400 #define EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2401 #define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x04000000 2402 #define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2403 #define EIM_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x05000000 2404 #define EIM_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 2405 #define EIM_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2406 2407 /* NAND_CLK_ROOT */ 2408 #define NAND_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2409 #define NAND_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2410 #define NAND_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000 2411 #define NAND_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x03000000 2412 #define NAND_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x04000000 2413 #define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000 2414 #define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 2415 #define NAND_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2416 2417 /* QSPI_CLK_ROOT */ 2418 #define QSPI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2419 #define QSPI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2420 #define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 2421 #define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x04000000 2422 #define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x01000000 2423 #define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 2424 #define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 2425 #define QSPI_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 2426 2427 /* USDHC1_CLK_ROOT */ 2428 #define USDHC1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2429 #define USDHC1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2430 #define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000 2431 #define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 2432 #define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 2433 #define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 2434 #define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 2435 #define USDHC1_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 2436 2437 /* USDHC2_CLK_ROOT */ 2438 #define USDHC2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2439 #define USDHC2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2440 #define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000 2441 #define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 2442 #define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 2443 #define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 2444 #define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 2445 #define USDHC2_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 2446 2447 /* USDHC3_CLK_ROOT */ 2448 #define USDHC3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2449 #define USDHC3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2450 #define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000 2451 #define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 2452 #define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000 2453 #define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000 2454 #define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 2455 #define USDHC3_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000 2456 2457 /* CAN1_CLK_ROOT */ 2458 #define CAN1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2459 #define CAN1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2460 #define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 2461 #define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 2462 #define CAN1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x04000000 2463 #define CAN1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 2464 #define CAN1_CLK_ROOT_FROM_EXT_CLK_1 0x06000000 2465 #define CAN1_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 2466 2467 /* CAN2_CLK_ROOT */ 2468 #define CAN2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2469 #define CAN2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2470 #define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000 2471 #define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 2472 #define CAN2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x04000000 2473 #define CAN2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 2474 #define CAN2_CLK_ROOT_FROM_EXT_CLK_1 0x06000000 2475 #define CAN2_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 2476 2477 /* I2C1_CLK_ROOT */ 2478 #define I2C1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2479 #define I2C1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2480 #define I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 2481 #define I2C1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 2482 #define I2C1_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 2483 #define I2C1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2484 #define I2C1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 2485 #define I2C1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 2486 2487 /* I2C2_CLK_ROOT */ 2488 #define I2C2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2489 #define I2C2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2490 #define I2C2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 2491 #define I2C2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 2492 #define I2C2_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 2493 #define I2C2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2494 #define I2C2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 2495 #define I2C2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 2496 2497 /* I2C3_CLK_ROOT */ 2498 #define I2C3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2499 #define I2C3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2500 #define I2C3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 2501 #define I2C3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 2502 #define I2C3_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 2503 #define I2C3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2504 #define I2C3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 2505 #define I2C3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 2506 2507 /* I2C4_CLK_ROOT */ 2508 #define I2C4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2509 #define I2C4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2510 #define I2C4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000 2511 #define I2C4_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000 2512 #define I2C4_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000 2513 #define I2C4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2514 #define I2C4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 2515 #define I2C4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000 2516 2517 /* UART1_CLK_ROOT */ 2518 #define UART1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2519 #define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2520 #define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2521 #define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 2522 #define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2523 #define UART1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2524 #define UART1_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2525 #define UART1_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 2526 2527 /* UART2_CLK_ROOT */ 2528 #define UART2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2529 #define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2530 #define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2531 #define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 2532 #define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2533 #define UART2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2534 #define UART2_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2535 #define UART2_CLK_ROOT_FROM_EXT_CLK_3 0x06000000 2536 2537 /* UART3_CLK_ROOT */ 2538 #define UART3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2539 #define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2540 #define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2541 #define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 2542 #define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2543 #define UART3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2544 #define UART3_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2545 #define UART3_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 2546 2547 /* UART4_CLK_ROOT */ 2548 #define UART4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2549 #define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2550 #define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2551 #define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 2552 #define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2553 #define UART4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2554 #define UART4_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2555 #define UART4_CLK_ROOT_FROM_EXT_CLK_3 0x06000000 2556 2557 /* UART5_CLK_ROOT */ 2558 #define UART5_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2559 #define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2560 #define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2561 #define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 2562 #define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2563 #define UART5_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2564 #define UART5_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2565 #define UART5_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 2566 2567 /* UART6_CLK_ROOT */ 2568 #define UART6_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2569 #define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2570 #define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2571 #define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 2572 #define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2573 #define UART6_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2574 #define UART6_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2575 #define UART6_CLK_ROOT_FROM_EXT_CLK_3 0x06000000 2576 2577 /* UART7_CLK_ROOT */ 2578 #define UART7_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2579 #define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2580 #define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2581 #define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000 2582 #define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2583 #define UART7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2584 #define UART7_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2585 #define UART7_CLK_ROOT_FROM_EXT_CLK_4 0x06000000 2586 2587 /* ECSPI1_CLK_ROOT */ 2588 #define ECSPI1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2589 #define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2590 #define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2591 #define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 2592 #define ECSPI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 2593 #define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 2594 #define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2595 #define ECSPI1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2596 2597 /* ECSPI2_CLK_ROOT */ 2598 #define ECSPI2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2599 #define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2600 #define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2601 #define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 2602 #define ECSPI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 2603 #define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 2604 #define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2605 #define ECSPI2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2606 2607 /* ECSPI3_CLK_ROOT */ 2608 #define ECSPI3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2609 #define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2610 #define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2611 #define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 2612 #define ECSPI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 2613 #define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 2614 #define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2615 #define ECSPI3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2616 2617 /* ECSPI4_CLK_ROOT */ 2618 #define ECSPI4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2619 #define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000 2620 #define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2621 #define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000 2622 #define ECSPI4_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000 2623 #define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000 2624 #define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000 2625 #define ECSPI4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2626 2627 /* PWM1_CLK_ROOT */ 2628 #define PWM1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2629 #define PWM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2630 #define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2631 #define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2632 #define PWM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2633 #define PWM1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2634 #define PWM1_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 2635 #define PWM1_CLK_ROOT_FROM_EXT_CLK_1 0x05000000 2636 2637 /* PWM2_CLK_ROOT */ 2638 #define PWM2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2639 #define PWM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2640 #define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2641 #define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2642 #define PWM2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2643 #define PWM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2644 #define PWM2_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 2645 #define PWM2_CLK_ROOT_FROM_EXT_CLK_1 0x05000000 2646 2647 /* PWM3_CLK_ROOT */ 2648 #define PWM3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2649 #define PWM3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2650 #define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2651 #define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2652 #define PWM3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2653 #define PWM3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2654 #define PWM3_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 2655 #define PWM3_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2656 2657 /* PWM4_CLK_ROOT */ 2658 #define PWM4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2659 #define PWM4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2660 #define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2661 #define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2662 #define PWM4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2663 #define PWM4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2664 #define PWM4_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 2665 #define PWM4_CLK_ROOT_FROM_EXT_CLK_2 0x05000000 2666 2667 /* FLEXTIMER1_CLK_ROOT */ 2668 #define FLEXTIMER1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2669 #define FLEXTIMER1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2670 #define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2671 #define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2672 #define FLEXTIMER1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2673 #define FLEXTIMER1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2674 #define FLEXTIMER1_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 2675 #define FLEXTIMER1_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 2676 2677 /* FLEXTIMER2_CLK_ROOT */ 2678 #define FLEXTIMER2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2679 #define FLEXTIMER2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2680 #define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2681 #define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2682 #define FLEXTIMER2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000 2683 #define FLEXTIMER2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000 2684 #define FLEXTIMER2_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 2685 #define FLEXTIMER2_CLK_ROOT_FROM_EXT_CLK_3 0x05000000 2686 2687 /* SIM1_CLK_ROOT */ 2688 #define SIM1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2689 #define SIM1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2690 #define SIM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2691 #define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2692 #define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 2693 #define SIM1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 2694 #define SIM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2695 #define SIM1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000 2696 2697 /* SIM2_CLK_ROOT */ 2698 #define SIM2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2699 #define SIM2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2700 #define SIM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2701 #define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2702 #define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 2703 #define SIM2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000 2704 #define SIM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000 2705 #define SIM2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000 2706 2707 /* GPT1_CLK_ROOT */ 2708 #define GPT1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2709 #define GPT1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 2710 #define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2711 #define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2712 #define GPT1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 2713 #define GPT1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 2714 #define GPT1_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 2715 #define GPT1_CLK_ROOT_FROM_EXT_CLK_1 0x07000000 2716 2717 /* GPT2_CLK_ROOT */ 2718 #define GPT2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2719 #define GPT2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 2720 #define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2721 #define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2722 #define GPT2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 2723 #define GPT2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 2724 #define GPT2_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 2725 #define GPT2_CLK_ROOT_FROM_EXT_CLK_2 0x07000000 2726 2727 /* GPT3_CLK_ROOT */ 2728 #define GPT3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2729 #define GPT3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 2730 #define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2731 #define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2732 #define GPT3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 2733 #define GPT3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 2734 #define GPT3_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 2735 #define GPT3_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 2736 2737 /* GPT4_CLK_ROOT */ 2738 #define GPT4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2739 #define GPT4_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 2740 #define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000 2741 #define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000 2742 #define GPT4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000 2743 #define GPT4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000 2744 #define GPT4_CLK_ROOT_FROM_REF_1M_CLK 0x05000000 2745 #define GPT4_CLK_ROOT_FROM_EXT_CLK_4 0x07000000 2746 2747 /* TRACE_CLK_ROOT */ 2748 #define TRACE_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2749 #define TRACE_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2750 #define TRACE_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2751 #define TRACE_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2752 #define TRACE_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 2753 #define TRACE_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 2754 #define TRACE_CLK_ROOT_FROM_EXT_CLK_1 0x06000000 2755 #define TRACE_CLK_ROOT_FROM_EXT_CLK_3 0x07000000 2756 2757 /* WDOG_CLK_ROOT */ 2758 #define WDOG_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2759 #define WDOG_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2760 #define WDOG_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2761 #define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD1_166M_CLK 0x07000000 2762 #define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2763 #define WDOG_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 2764 #define WDOG_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000 2765 #define WDOG_CLK_ROOT_FROM_REF_1M_CLK 0x06000000 2766 2767 /* CSI_MCLK_CLK_ROOT */ 2768 #define CSI_MCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2769 #define CSI_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2770 #define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2771 #define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2772 #define CSI_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 2773 #define CSI_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2774 #define CSI_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2775 #define CSI_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2776 2777 /* AUDIO_MCLK_CLK_ROOT */ 2778 #define AUDIO_MCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2779 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000 2780 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000 2781 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000 2782 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000 2783 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2784 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2785 #define AUDIO_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000 2786 2787 /* WRCLK_CLK_ROOT */ 2788 #define WRCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000 2789 #define WRCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000 2790 #define WRCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x04000000 2791 #define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000 2792 #define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000 2793 #define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x06000000 2794 #define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x01000000 2795 #define WRCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x03000000 2796 2797 /* IPP_DO_CLKO1 */ 2798 #define IPP_DO_CLKO1_FROM_OSC_24M_CLK 0x00000000 2799 #define IPP_DO_CLKO1_FROM_PLL_DRAM_MAIN_533M_CLK 0x06000000 2800 #define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000 2801 #define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_240M_CLK 0x02000000 2802 #define IPP_DO_CLKO1_FROM_PLL_SYS_PFD0_196M_CLK 0x03000000 2803 #define IPP_DO_CLKO1_FROM_PLL_SYS_PFD3_CLK 0x04000000 2804 #define IPP_DO_CLKO1_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000 2805 #define IPP_DO_CLKO1_FROM_REF_1M_CLK 0x07000000 2806 2807 /* IPP_DO_CLKO2 */ 2808 #define IPP_DO_CLKO2_FROM_OSC_24M_CLK 0x00000000 2809 #define IPP_DO_CLKO2_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000 2810 #define IPP_DO_CLKO2_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000 2811 #define IPP_DO_CLKO2_FROM_PLL_SYS_PFD1_166M_CLK 0x03000000 2812 #define IPP_DO_CLKO2_FROM_PLL_SYS_PFD4_CLK 0x04000000 2813 #define IPP_DO_CLKO2_FROM_PLL_AUDIO_MAIN_CLK 0x05000000 2814 #define IPP_DO_CLKO2_FROM_PLL_VIDEO_MAIN_CLK 0x06000000 2815 #define IPP_DO_CLKO2_FROM_OSC_32K_CLK 0x07000000 2816 2817 #endif 2818
