1 /** @file 2 3 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR> 4 This program and the accompanying materials 5 are licensed and made available under the terms and conditions of the BSD License 6 which accompanies this distribution. The full text of the license may be found at 7 http://opensource.org/licenses/bsd-license.php. 8 9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11 12 **/ 13 14 #ifndef _EMMC_HCI_H_ 15 #define _EMMC_HCI_H_ 16 17 // 18 // EMMC Host Controller MMIO Register Offset 19 // 20 #define EMMC_HC_SDMA_ADDR 0x00 21 #define EMMC_HC_ARG2 0x00 22 #define EMMC_HC_BLK_SIZE 0x04 23 #define EMMC_HC_BLK_COUNT 0x06 24 #define EMMC_HC_ARG1 0x08 25 #define EMMC_HC_TRANS_MOD 0x0C 26 #define EMMC_HC_COMMAND 0x0E 27 #define EMMC_HC_RESPONSE 0x10 28 #define EMMC_HC_BUF_DAT_PORT 0x20 29 #define EMMC_HC_PRESENT_STATE 0x24 30 #define EMMC_HC_HOST_CTRL1 0x28 31 #define EMMC_HC_POWER_CTRL 0x29 32 #define EMMC_HC_BLK_GAP_CTRL 0x2A 33 #define EMMC_HC_WAKEUP_CTRL 0x2B 34 #define EMMC_HC_CLOCK_CTRL 0x2C 35 #define EMMC_HC_TIMEOUT_CTRL 0x2E 36 #define EMMC_HC_SW_RST 0x2F 37 #define EMMC_HC_NOR_INT_STS 0x30 38 #define EMMC_HC_ERR_INT_STS 0x32 39 #define EMMC_HC_NOR_INT_STS_EN 0x34 40 #define EMMC_HC_ERR_INT_STS_EN 0x36 41 #define EMMC_HC_NOR_INT_SIG_EN 0x38 42 #define EMMC_HC_ERR_INT_SIG_EN 0x3A 43 #define EMMC_HC_AUTO_CMD_ERR_STS 0x3C 44 #define EMMC_HC_HOST_CTRL2 0x3E 45 #define EMMC_HC_CAP 0x40 46 #define EMMC_HC_MAX_CURRENT_CAP 0x48 47 #define EMMC_HC_FORCE_EVT_AUTO_CMD 0x50 48 #define EMMC_HC_FORCE_EVT_ERR_INT 0x52 49 #define EMMC_HC_ADMA_ERR_STS 0x54 50 #define EMMC_HC_ADMA_SYS_ADDR 0x58 51 #define EMMC_HC_PRESET_VAL 0x60 52 #define EMMC_HC_SHARED_BUS_CTRL 0xE0 53 #define EMMC_HC_SLOT_INT_STS 0xFC 54 #define EMMC_HC_CTRL_VER 0xFE 55 56 // 57 // The transfer modes supported by SD Host Controller 58 // Simplified Spec 3.0 Table 1-2 59 // 60 typedef enum { 61 EmmcNoData, 62 EmmcPioMode, 63 EmmcSdmaMode, 64 EmmcAdmaMode 65 } EMMC_HC_TRANSFER_MODE; 66 67 // 68 // The maximum data length of each descriptor line 69 // 70 #define ADMA_MAX_DATA_PER_LINE 0x10000 71 #define EMMC_SDMA_BOUNDARY 512 * 1024 72 #define EMMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1)) 73 74 typedef enum { 75 EmmcCommandTypeBc, // Broadcast commands, no response 76 EmmcCommandTypeBcr, // Broadcast commands with response 77 EmmcCommandTypeAc, // Addressed(point-to-point) commands 78 EmmcCommandTypeAdtc // Addressed(point-to-point) data transfer commands 79 } EMMC_COMMAND_TYPE; 80 81 typedef enum { 82 EmmcResponceTypeR1, 83 EmmcResponceTypeR1b, 84 EmmcResponceTypeR2, 85 EmmcResponceTypeR3, 86 EmmcResponceTypeR4, 87 EmmcResponceTypeR5, 88 EmmcResponceTypeR5b, 89 EmmcResponceTypeR6, 90 EmmcResponceTypeR7 91 } EMMC_RESPONSE_TYPE; 92 93 typedef struct _EMMC_COMMAND_BLOCK { 94 UINT16 CommandIndex; 95 UINT32 CommandArgument; 96 UINT32 CommandType; // One of the EMMC_COMMAND_TYPE values 97 UINT32 ResponseType; // One of the EMMC_RESPONSE_TYPE values 98 } EMMC_COMMAND_BLOCK; 99 100 typedef struct _EMMC_STATUS_BLOCK { 101 UINT32 Resp0; 102 UINT32 Resp1; 103 UINT32 Resp2; 104 UINT32 Resp3; 105 } EMMC_STATUS_BLOCK; 106 107 typedef struct _EMMC_COMMAND_PACKET { 108 UINT64 Timeout; 109 EMMC_COMMAND_BLOCK *EmmcCmdBlk; 110 EMMC_STATUS_BLOCK *EmmcStatusBlk; 111 VOID *InDataBuffer; 112 VOID *OutDataBuffer; 113 UINT32 InTransferLength; 114 UINT32 OutTransferLength; 115 } EMMC_COMMAND_PACKET; 116 117 #pragma pack(1) 118 119 typedef struct { 120 UINT32 Valid:1; 121 UINT32 End:1; 122 UINT32 Int:1; 123 UINT32 Reserved:1; 124 UINT32 Act:2; 125 UINT32 Reserved1:10; 126 UINT32 Length:16; 127 UINT32 Address; 128 } EMMC_HC_ADMA_DESC_LINE; 129 130 typedef struct { 131 UINT32 TimeoutFreq:6; // bit 0:5 132 UINT32 Reserved:1; // bit 6 133 UINT32 TimeoutUnit:1; // bit 7 134 UINT32 BaseClkFreq:8; // bit 8:15 135 UINT32 MaxBlkLen:2; // bit 16:17 136 UINT32 BusWidth8:1; // bit 18 137 UINT32 Adma2:1; // bit 19 138 UINT32 Reserved2:1; // bit 20 139 UINT32 HighSpeed:1; // bit 21 140 UINT32 Sdma:1; // bit 22 141 UINT32 SuspRes:1; // bit 23 142 UINT32 Voltage33:1; // bit 24 143 UINT32 Voltage30:1; // bit 25 144 UINT32 Voltage18:1; // bit 26 145 UINT32 Reserved3:1; // bit 27 146 UINT32 SysBus64:1; // bit 28 147 UINT32 AsyncInt:1; // bit 29 148 UINT32 SlotType:2; // bit 30:31 149 UINT32 Sdr50:1; // bit 32 150 UINT32 Sdr104:1; // bit 33 151 UINT32 Ddr50:1; // bit 34 152 UINT32 Reserved4:1; // bit 35 153 UINT32 DriverTypeA:1; // bit 36 154 UINT32 DriverTypeC:1; // bit 37 155 UINT32 DriverTypeD:1; // bit 38 156 UINT32 DriverType4:1; // bit 39 157 UINT32 TimerCount:4; // bit 40:43 158 UINT32 Reserved5:1; // bit 44 159 UINT32 TuningSDR50:1; // bit 45 160 UINT32 RetuningMod:2; // bit 46:47 161 UINT32 ClkMultiplier:8; // bit 48:55 162 UINT32 Reserved6:7; // bit 56:62 163 UINT32 Hs400:1; // bit 63 164 } EMMC_HC_SLOT_CAP; 165 166 #pragma pack() 167 168 /** 169 Software reset the specified EMMC host controller and enable all interrupts. 170 171 @param[in] Bar The mmio base address of the slot to be accessed. 172 173 @retval EFI_SUCCESS The software reset executes successfully. 174 @retval Others The software reset fails. 175 176 **/ 177 EFI_STATUS 178 EmmcPeimHcReset ( 179 IN UINTN Bar 180 ); 181 182 /** 183 Set all interrupt status bits in Normal and Error Interrupt Status Enable 184 register. 185 186 @param[in] Bar The mmio base address of the slot to be accessed. 187 188 @retval EFI_SUCCESS The operation executes successfully. 189 @retval Others The operation fails. 190 191 **/ 192 EFI_STATUS 193 EmmcPeimHcEnableInterrupt ( 194 IN UINTN Bar 195 ); 196 197 /** 198 Get the capability data from the specified slot. 199 200 @param[in] Bar The mmio base address of the slot to be accessed. 201 @param[out] Capability The buffer to store the capability data. 202 203 @retval EFI_SUCCESS The operation executes successfully. 204 @retval Others The operation fails. 205 206 **/ 207 EFI_STATUS 208 EmmcPeimHcGetCapability ( 209 IN UINTN Bar, 210 OUT EMMC_HC_SLOT_CAP *Capability 211 ); 212 213 /** 214 Detect whether there is a EMMC card attached at the specified EMMC host controller 215 slot. 216 217 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details. 218 219 @param[in] Bar The mmio base address of the slot to be accessed. 220 221 @retval EFI_SUCCESS There is a EMMC card attached. 222 @retval EFI_NO_MEDIA There is not a EMMC card attached. 223 @retval Others The detection fails. 224 225 **/ 226 EFI_STATUS 227 EmmcPeimHcCardDetect ( 228 IN UINTN Bar 229 ); 230 231 /** 232 Initial EMMC host controller with lowest clock frequency, max power and max timeout value 233 at initialization. 234 235 @param[in] Bar The mmio base address of the slot to be accessed. 236 237 @retval EFI_SUCCESS The host controller is initialized successfully. 238 @retval Others The host controller isn't initialized successfully. 239 240 **/ 241 EFI_STATUS 242 EmmcPeimHcInitHost ( 243 IN UINTN Bar 244 ); 245 246 /** 247 Send command SWITCH to the EMMC device to switch the mode of operation of the 248 selected Device or modifies the EXT_CSD registers. 249 250 Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details. 251 252 @param[in] Slot The slot number of the Emmc card to send the command to. 253 @param[in] Access The access mode of SWTICH command. 254 @param[in] Index The offset of the field to be access. 255 @param[in] Value The value to be set to the specified field of EXT_CSD register. 256 @param[in] CmdSet The value of CmdSet field of EXT_CSD register. 257 258 @retval EFI_SUCCESS The operation is done correctly. 259 @retval Others The operation fails. 260 261 **/ 262 EFI_STATUS 263 EmmcPeimSwitch ( 264 IN EMMC_PEIM_HC_SLOT *Slot, 265 IN UINT8 Access, 266 IN UINT8 Index, 267 IN UINT8 Value, 268 IN UINT8 CmdSet 269 ); 270 271 /** 272 Send command SET_BLOCK_COUNT to the addressed EMMC device to set the number of 273 blocks for the following block read/write cmd. 274 275 Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details. 276 277 @param[in] Slot The slot number of the Emmc card to send the command to. 278 @param[in] BlockCount The number of the logical block to access. 279 280 @retval EFI_SUCCESS The operation is done correctly. 281 @retval Others The operation fails. 282 283 **/ 284 EFI_STATUS 285 EmmcPeimSetBlkCount ( 286 IN EMMC_PEIM_HC_SLOT *Slot, 287 IN UINT16 BlockCount 288 ); 289 290 /** 291 Send command READ_MULTIPLE_BLOCK/WRITE_MULTIPLE_BLOCK to the addressed EMMC device 292 to read/write the specified number of blocks. 293 294 Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details. 295 296 @param[in] Slot The slot number of the Emmc card to send the command to. 297 @param[in] Lba The logical block address of starting access. 298 @param[in] BlockSize The block size of specified EMMC device partition. 299 @param[in] Buffer The pointer to the transfer buffer. 300 @param[in] BufferSize The size of transfer buffer. 301 @param[in] IsRead Boolean to show the operation direction. 302 303 @retval EFI_SUCCESS The operation is done correctly. 304 @retval Others The operation fails. 305 306 **/ 307 EFI_STATUS 308 EmmcPeimRwMultiBlocks ( 309 IN EMMC_PEIM_HC_SLOT *Slot, 310 IN EFI_LBA Lba, 311 IN UINT32 BlockSize, 312 IN VOID *Buffer, 313 IN UINTN BufferSize, 314 IN BOOLEAN IsRead 315 ); 316 317 /** 318 Execute EMMC device identification procedure. 319 320 Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details. 321 322 @param[in] Slot The slot number of the Emmc card to send the command to. 323 324 @retval EFI_SUCCESS There is a EMMC card. 325 @retval Others There is not a EMMC card. 326 327 **/ 328 EFI_STATUS 329 EmmcPeimIdentification ( 330 IN EMMC_PEIM_HC_SLOT *Slot 331 ); 332 333 /** 334 Free the resource used by the TRB. 335 336 @param[in] Trb The pointer to the EMMC_TRB instance. 337 338 **/ 339 VOID 340 EmmcPeimFreeTrb ( 341 IN EMMC_TRB *Trb 342 ); 343 344 #endif 345 346
