1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2016 Freescale Semiconductor 4 */ 5 6 #ifndef __LS1046ARDB_H__ 7 #define __LS1046ARDB_H__ 8 9 #include "ls1046a_common.h" 10 11 #define CONFIG_SYS_CLK_FREQ 100000000 12 #define CONFIG_DDR_CLK_FREQ 100000000 13 14 #define CONFIG_LAYERSCAPE_NS_ACCESS 15 #define CONFIG_MISC_INIT_R 16 17 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 18 /* Physical Memory Map */ 19 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 20 #define CONFIG_NR_DRAM_BANKS 2 21 22 #define CONFIG_DDR_SPD 23 #define SPD_EEPROM_ADDRESS 0x51 24 #define CONFIG_SYS_SPD_BUS_NUM 0 25 26 #define CONFIG_DDR_ECC 27 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 28 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 29 #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ 30 #ifndef CONFIG_SPL 31 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ 32 #endif 33 34 #ifdef CONFIG_RAMBOOT_PBL 35 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg 36 #endif 37 38 #ifdef CONFIG_SD_BOOT 39 #ifdef CONFIG_EMMC_BOOT 40 #define CONFIG_SYS_FSL_PBL_RCW \ 41 board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg 42 #else 43 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg 44 #endif 45 #endif 46 47 #ifndef SPL_NO_IFC 48 /* IFC */ 49 #define CONFIG_FSL_IFC 50 /* 51 * NAND Flash Definitions 52 */ 53 #define CONFIG_NAND_FSL_IFC 54 #endif 55 56 #define CONFIG_SYS_NAND_BASE 0x7e800000 57 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 58 59 #define CONFIG_SYS_NAND_CSPR_EXT (0x0) 60 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 61 | CSPR_PORT_SIZE_8 \ 62 | CSPR_MSEL_NAND \ 63 | CSPR_V) 64 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 65 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 66 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 67 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ 68 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 69 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 70 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ 71 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 72 73 #define CONFIG_SYS_NAND_ONFI_DETECTION 74 75 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ 76 FTIM0_NAND_TWP(0x18) | \ 77 FTIM0_NAND_TWCHT(0x7) | \ 78 FTIM0_NAND_TWH(0xa)) 79 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 80 FTIM1_NAND_TWBE(0x39) | \ 81 FTIM1_NAND_TRR(0xe) | \ 82 FTIM1_NAND_TRP(0x18)) 83 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ 84 FTIM2_NAND_TREH(0xa) | \ 85 FTIM2_NAND_TWHRE(0x1e)) 86 #define CONFIG_SYS_NAND_FTIM3 0x0 87 88 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 89 #define CONFIG_SYS_MAX_NAND_DEVICE 1 90 #define CONFIG_MTD_NAND_VERIFY_WRITE 91 92 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 93 94 /* 95 * CPLD 96 */ 97 #define CONFIG_SYS_CPLD_BASE 0x7fb00000 98 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE 99 100 #define CONFIG_SYS_CPLD_CSPR_EXT (0x0) 101 #define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ 102 CSPR_PORT_SIZE_8 | \ 103 CSPR_MSEL_GPCM | \ 104 CSPR_V) 105 #define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) 106 #define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16) 107 108 /* CPLD Timing parameters for IFC GPCM */ 109 #define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 110 FTIM0_GPCM_TEADC(0x0e) | \ 111 FTIM0_GPCM_TEAHC(0x0e)) 112 #define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 113 FTIM1_GPCM_TRAD(0x3f)) 114 #define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ 115 FTIM2_GPCM_TCH(0xf) | \ 116 FTIM2_GPCM_TWP(0x3E)) 117 #define CONFIG_SYS_CPLD_FTIM3 0x0 118 119 /* IFC Timing Params */ 120 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 121 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 122 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 123 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 124 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 125 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 126 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 127 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 128 129 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT 130 #define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR 131 #define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK 132 #define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR 133 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 134 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 135 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 136 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 137 138 /* EEPROM */ 139 #define CONFIG_ID_EEPROM 140 #define CONFIG_SYS_I2C_EEPROM_NXID 141 #define CONFIG_SYS_EEPROM_BUS_NUM 0 142 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 143 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 144 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 145 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 146 #define I2C_RETIMER_ADDR 0x18 147 148 /* PMIC */ 149 #define CONFIG_POWER 150 #ifdef CONFIG_POWER 151 #define CONFIG_POWER_I2C 152 #endif 153 154 /* 155 * Environment 156 */ 157 #ifndef SPL_NO_ENV 158 #define CONFIG_ENV_OVERWRITE 159 #endif 160 161 #if defined(CONFIG_SD_BOOT) 162 #define CONFIG_SYS_MMC_ENV_DEV 0 163 #define CONFIG_ENV_OFFSET (3 * 1024 * 1024) 164 #define CONFIG_ENV_SIZE 0x2000 165 #else 166 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 167 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ 168 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ 169 #endif 170 171 #define AQR105_IRQ_MASK 0x80000000 172 /* FMan */ 173 #ifndef SPL_NO_FMAN 174 175 #ifdef CONFIG_NET 176 #define CONFIG_PHY_REALTEK 177 #endif 178 179 #ifdef CONFIG_SYS_DPAA_FMAN 180 #define CONFIG_FMAN_ENET 181 #define CONFIG_PHY_AQUANTIA 182 #define CONFIG_PHYLIB_10G 183 #define RGMII_PHY1_ADDR 0x1 184 #define RGMII_PHY2_ADDR 0x2 185 186 #define SGMII_PHY1_ADDR 0x3 187 #define SGMII_PHY2_ADDR 0x4 188 189 #define FM1_10GEC1_PHY_ADDR 0x0 190 191 #define FDT_SEQ_MACADDR_FROM_ENV 192 193 #define CONFIG_ETHPRIME "FM1@DTSEC3" 194 #endif 195 196 #endif 197 198 /* QSPI device */ 199 #ifndef SPL_NO_QSPI 200 #ifdef CONFIG_FSL_QSPI 201 #define CONFIG_SPI_FLASH_SPANSION 202 #define FSL_QSPI_FLASH_SIZE (1 << 26) 203 #define FSL_QSPI_FLASH_NUM 2 204 #endif 205 #endif 206 207 #ifndef SPL_NO_MISC 208 #undef CONFIG_BOOTCOMMAND 209 #if defined(CONFIG_QSPI_BOOT) 210 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ 211 "env exists secureboot && esbc_halt;;" 212 #elif defined(CONFIG_SD_BOOT) 213 #define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ 214 "env exists secureboot && esbc_halt;" 215 #endif 216 #endif 217 218 #include <asm/fsl_secure_boot.h> 219 220 #endif /* __LS1046ARDB_H__ */ 221
